When you connect parallel voltage sources, the nominal voltage remains identical to a single source, but the total current-delivery capacity (Amp-hours) and maximum continuous discharge current add together. For a maker building a portable power bank, a robotics power bus, or an off-grid 12V buffer, this topology is the standard method for scaling up runtime and surge capability without altering the downstream DC-DC converter's input voltage requirements.
This guide breaks down the exact node behavior, failure extremes, and a real-world bench test procedure for a 2P lithium-ion cell configuration.
The Parallel Topology: Node Labels and Element Behavior
In a parallel configuration, all positive terminals tie to a single common node, and all negative terminals tie to another. Let's define our nodes:
- Node V+ (Positive Bus): The junction where all source anodes (or positive supply outputs) meet. The voltage here is dictated by the highest-potential source in the bank.
- Node GND (Negative Bus): The junction where all source cathodes (or negative/ground returns) meet. This is your 0V reference.
According to Kirchhoff's Current Law (KCL), the total current delivered to the load at Node V+ is the sum of the individual currents supplied by each source ($I_{total} = I_1 + I_2 + ... + I_n$). However, how that current divides depends entirely on the internal resistance ($R_{int}$) and the exact open-circuit voltage ($V_{oc}$) of each source.
Behavior Matrix: What Changes When One Element Shifts?
| Element Change | System Effect at Node V+ | Current Distribution Shift |
|---|---|---|
| Cell 1 $V_{oc}$ drops by 0.2V | Total $V_{oc}$ sags slightly toward Cell 2's potential. | Cell 2 sources the majority of the load current; Cell 1 may actually become a load (sink current) if its voltage drops below the bus voltage. |
| Cell 1 $R_{int}$ doubles (aging) | Overall bank equivalent $R_{int}$ increases marginally. | Cell 2 supplies a larger share of the load current. Cell 2 will heat up and age faster, creating a cascading imbalance. |
| Load current doubles | Bus voltage sags according to $V_{sag} = I_{load} \times R_{eq}$. | Current splits proportionally based on the inverse ratio of each cell's internal resistance. |
Why Parallel Over Series? (And What Breaks at the Extremes)
Why choose parallel voltage sources instead of wiring them in series? The decision comes down to your downstream power electronics.
| Criteria | Parallel Topology | Series Topology |
|---|---|---|
| Voltage Output | Remains constant ($V_{nom}$) | Additive ($V_1 + V_2 + ...$) |
| Current Capacity | Additive ($I_{max1} + I_{max2}$) | Limited by the weakest cell |
| Best Use Case | Extending runtime for 5V USB or 12V nominal systems. | Driving high-voltage motor controllers or grid-tie inverters. |
| BMS Complexity | Simple (1S BMS monitors the whole bank as one cell). | Complex (Requires cell-by-cell balancing and over-voltage protection). |
Failure Modes at the Extremes
Understanding what happens when a parallel bank breaks is critical for designing proper protection circuits.
Extreme 1: One Source Opens (Open Circuit)
If a cell's internal fuse blows or a weld tab breaks, the remaining sources instantly take 100% of the load. If your load is pulling 20A from a 2P bank designed for 10A per cell, the surviving cell is now pulling 20A. If this exceeds its maximum continuous discharge rating, it will overheat, vent, and potentially fail catastrophically.
Extreme 2: One Source Shorts (Dead Short)
If a cell develops an internal dendrite short, its voltage collapses to near 0V. The remaining healthy cells will dump their maximum possible short-circuit current (often 50A to 100A+ per cell) directly into the failed cell through Node V+. This massive, uncontrolled circulating current causes rapid thermal runaway. This is why high-reliability parallel packs use cell-level fuses or specialized BMS architectures.
Design Walkthrough: Building and Testing a 2P 18650 Pack
Let's design a 2-parallel (2P) battery bank to power a portable 12V-to-5V high-current USB-C PD router setup. We need high continuous current and long runtime.
Selected Components:
- Cells: 2x Molicel P28A (18650 format). Nominal 3.7V, 2800mAh capacity, 25A max continuous discharge, ~20mΩ typical internal resistance.
- Bank Specs: 3.7V nominal, 5600mAh total capacity, ~10mΩ equivalent internal resistance ($20m\Omega / 2$).
- Holder: 2-slot 18650 parallel battery holder with thick spring contacts (the breadboard equivalent for raw cells).
Step-by-Step Bench Testing Procedure
Before you spot-weld nickel strips or solder pigtails, you must verify the cells behave correctly in parallel on the bench. For deeper theory on battery configurations, consult the All About Circuits DC Textbook.
- Voltage Matching: Using a 4-wire multimeter, measure the open-circuit voltage of both P28A cells. They must be within 0.05V of each other (e.g., Cell 1: 3.92V, Cell 2: 3.95V). If they are further apart, charge or discharge them individually until they match. Connecting mismatched cells will cause an immediate, damaging spark and high circulating current.
- Insertion and Bus Verification: Insert both cells into the parallel holder, ensuring correct polarity. Set your multimeter to DC Voltage and probe the holder's V+ and GND terminals. You should read the matched voltage (e.g., ~3.93V).
- Resting Current Check: Switch your multimeter to the 10A current range. Place the probes in series between the V+ node of one cell and the V+ node of the holder. If the cells are perfectly matched, the circulating current should read 0.00A to 0.05A. If it reads higher, remove the cells and re-match their voltages.
- Load Sag Test (Calculating Real $R_{int}$): Connect a known resistive load to the holder. A 2Ω, 50W power resistor is ideal.
- Measure the open-circuit voltage ($V_{oc}$) before connecting the load (e.g., 3.93V).
- Connect the load and immediately measure the loaded voltage ($V_{load}$) and the current ($I_{load}$). Let's say $V_{load}$ drops to 3.75V and $I_{load}$ is 1.85A.
- Calculate the bank's equivalent internal resistance: $R_{eq} = (V_{oc} - V_{load}) / I_{load} = (3.93 - 3.75) / 1.85 = 0.097\Omega$ (97mΩ).
- Thermal Verification: Let the load run for 5 minutes. Use an IR thermometer to check the cell casings. Both cells should heat up evenly. If one cell is significantly hotter, its internal resistance is higher, and it is hogging less of the load while the other cell overworks. Discard the mismatched cell.
Frequently Asked Questions
Can you connect parallel voltage sources with different voltages?
Technically yes, but practically it is a bad idea for batteries and unregulated supplies. If you parallel a 4.2V fully charged Li-ion cell with a 3.0V depleted cell, the 1.2V difference will drive a massive current from the full cell into the empty cell, limited only by their internal resistances and the wire resistance. This circulating current wastes energy as heat and can easily exceed the safe charge rate of the depleted cell, causing a fire. For bench power supplies, connecting different voltages in parallel will cause the higher-voltage supply to backfeed the lower-voltage supply, potentially damaging its output stage unless it has reverse-current protection.
Do parallel voltage sources need diodes to prevent backfeeding?
For bench power supplies or solar panels, yes. We use 'OR-ing' diodes (or ideal diode controllers) on the positive output of each source so that a failed shorted supply doesn't drag the whole bus down, and to prevent backfeeding. However, for battery packs, we almost never use series diodes. A standard silicon diode drops ~0.7V, and a Schottky drops ~0.3V. At 10A of load current, a 0.3V drop wastes 3W of power as heat and artificially lowers your battery bank's usable voltage window. Instead of diodes, battery designers rely on cell-matching, fuses, and active BMS MOSFETs to manage faults.
How do you calculate the total internal resistance of parallel sources?
The internal resistance of parallel voltage sources combines exactly like standard parallel resistors. If you have two identical cells, each with an internal resistance of $R$, the total equivalent resistance is $R / 2$. If you have mismatched cells with resistances $R_1$ and $R_2$, the formula is $R_{eq} = (R_1 \times R_2) / (R_1 + R_2)$. This lower equivalent resistance is exactly why parallel banks experience less voltage sag under heavy loads compared to a single cell.
