The P-channel MOSFET symbol in standard US schematics (IEEE 315) features a circle with an outward-pointing arrow on the source lead, indicating conventional current flows from Source to Drain. In the IEC 60617 standard common in Europe, it uses a rectangular block with a specific polarity marker. Below is the complete reference for schematic symbols, physical package pinouts, and standard variants to keep your bench work and PCB designs accurate.

P-Channel MOSFET Schematic Symbols & Pinout Reference

When reading a schematic, the P-channel symbol tells you exactly how the device behaves and how it must be biased. Unlike N-channel MOSFETs which require a positive gate-to-source voltage to turn on, a P-channel device requires the gate to be pulled below the source voltage (a negative Vgs).
Symbol Element Visual Representation Electrical Meaning & Practical Rule
Gate (G) Line perpendicular to channel, separated by a gap (insulation) High impedance input. For P-ch, pull to GND (or lower than Source) to turn ON. Never leave floating; use a 10kΩ-100kΩ pull-up resistor to Source to prevent erratic switching.
Source (S) & Arrow Line with an arrow pointing OUT (away from channel) Indicates conventional current direction (Source to Drain). The arrow is on the Source lead in IEEE symbols. Connect to the higher voltage rail (e.g., VCC/Battery+).
Drain (D) Line opposite the Source, no arrow Current exit point. Connects to the load. In high-side switching, the load sits between the Drain and GND.
Channel Line Broken/dashed line (Enhancement) vs Solid line (Depletion) 99% of modern P-ch MOSFETs (like the IRF9540N or Si2301) are enhancement mode (dashed line), meaning they are normally OFF until a negative Vgs is applied.
Body / Parasitic Diode Triangle and bar bridging Drain and Source Intrinsic PN junction. For P-ch, the Anode is at the Drain and Cathode is at the Source. If wired backward, this diode conducts continuously, bypassing the MOSFET channel.

Physical Package Pinouts: TO-220, SOT-23, and SOIC

Schematic symbols are only half the battle; mapping them to physical silicon is where most bench mistakes happen. Pinouts change drastically depending on the package outline. Never assume Pin 1 is always the Gate or that the pin sequence remains constant across form factors.
Package Type Common Part Example Pin 1 Pin 2 Pin 3 Tab / Exposed Pad
TO-220 (Through-hole) IRF9540N (55V, 17A) Gate Drain Source Drain (Thermal/Electrical)
SOT-23 (SMD, 3-pin) Si2301 (20V, 2.3A) Gate Source Drain N/A
SOIC-8 (SMD, 8-pin) FDS6679 (30V, 9A) Source Source Source Drain (Pins 5-8 tied)
DPAK / TO-252 (SMD) STD10PF06 (60V, 10A) Gate Source Drain Drain (Large solder pad)
CRITICAL PINOUT TRAP: The SOT-23 package pinout is a frequent source of fried boards. While the TO-220 sequence is Gate-Drain-Source, the SOT-23 sequence is Gate-Source-Drain. If you design a PCB footprint assuming SOT-23 matches TO-220, you will short the Gate to the Drain or apply full VCC to the Gate oxide, instantly destroying the silicon. Always verify against the specific manufacturer's datasheet, such as the Nexperia SOT-23 package outline.

Rows People Get Wrong & Faded Marking Identification

Even experienced builders misinterpret specific aspects of the P-channel symbol and physical components. Here are the most common errors and how to resolve them.

1. The Body Diode Direction Confusion

People often remember that MOSFETs have a body diode but forget its orientation. In a P-channel MOSFET, the body diode points from Drain to Source (Anode at Drain, Cathode at Source). This means the diode naturally conducts if the Drain voltage is higher than the Source voltage. In a high-side switch configuration, the Source must connect to the positive supply rail and the Drain to the load. If you swap them, the body diode will forward-bias immediately, and the load will remain powered even when the MOSFET gate is driven high (OFF).

2. Gate Threshold vs. Full Enhancement

Datasheets list a Gate-Source Threshold Voltage (Vgs(th)), often around -2.0V to -4.0V for standard parts, or -0.7V for logic-level parts. A common mistake is assuming Vgs(th) is the voltage required to turn the MOSFET fully ON. It is not; it is merely the voltage where the device begins to conduct a tiny leakage current (usually 250µA). To achieve the low Rds(on) stated in the datasheet, you must drive the gate to the full test Vgs, typically -10V for standard parts or -4.5V for logic-level parts. For exact parameters, refer to the ON Semiconductor IRF9540N datasheet.

3. Identifying Faded or Unmarked SMD MOSFETs

SOT-23 and SOIC-8 MOSFETs often have cryptic 3-letter codes that rub off during rework or are too small to read. You can definitively identify a P-channel MOSFET and map its pins using a digital multimeter in Diode Test mode:

  • Find the Body Diode: Place the Red probe on one pin and Black on another. If you read a forward voltage drop (0.4V to 0.7V), you have found the Drain (Red probe) and Source (Black probe). Swap probes; it should read 'OL' (Open Loop).
  • Find the Gate: The remaining pin is the Gate. Testing between the Gate and either Drain or Source should read 'OL' in both directions due to the insulated silicon dioxide layer.
  • Confirm P-Channel: If the Red probe on Pin A and Black probe on Pin B yields a diode drop, and Pin A connects to your circuit's load side while Pin B connects to VCC, it is a P-channel device.

Standard Variants: IEEE/ANSI vs. IEC 60617

Schematic symbols are not globally uniform. Depending on where your CAD software was developed or where your engineering team is located, you will encounter two distinct standards for drawing the P-channel MOSFET.

IEEE 315 / ANSI Y32.2 (The 'Bug' Symbol)

Dominant in the US, Canada, and most hobbyist/academic environments. This is the traditional symbol featuring the circle, the three leads, and the distinct outward-pointing arrow on the Source. The gap between the Gate and the channel line visually represents the insulated gate. This standard is highly intuitive because the physical geometry of the symbol loosely mimics the physical structure of the semiconductor junctions. Resources like the All About Circuits semiconductor textbook rely heavily on this format for teaching.

IEC 60617 (The Rectangular Block Symbol)

Standard in Europe, international industrial schematics, and heavy machinery documentation. The IEC standard abandons the 'bug' shape in favor of a rectangular envelope. The P-channel MOSFET is drawn as a rectangle with a specific polarity marker (usually a small arrow or line indicating P-type material) and connection points labeled G, D, and S. While less visually intuitive for beginners learning semiconductor physics, the IEC standard scales much better for complex VLSI and dense industrial control schematics where drawing hundreds of 'bug' symbols would clutter the drafting sheet.

When designing schematics in tools like KiCad or Altium, ensure your symbol library matches the expectation of your fabrication house or client. Mixing IEEE and IEC symbols on the same schematic sheet is considered poor drafting practice and can lead to misinterpretation during board bring-up.