The input resistance of an op amp is the equivalent DC resistance seen looking into its inverting and non-inverting input terminals. In real-world silicon, this value typically ranges from 300 kΩ for older bipolar designs to over 1 TΩ (1012 Ω) for modern CMOS and JFET devices. If your source impedance is high and your op amp’s input resistance is too low, you will suffer severe signal attenuation and DC offset errors due to input bias currents.

This guide cuts through the semiconductor physics and gives you the exact decision paths, biasing rules, and default part numbers you need to select the right op amp for your specific source impedance.

Op Amp Pinout and the Input Stage Architecture

To understand input resistance, you must look at the physical pins and the internal differential pair. The industry-standard 8-pin DIP (Dual In-line Package) op amp follows this pinout:

  • Pin 1 & 5: Offset Null (used for trimming DC offset, often left unconnected)
  • Pin 2: Inverting Input (IN-)
  • Pin 3: Non-Inverting Input (IN+)
  • Pin 4: V- (Negative Supply or Ground in single-supply)
  • Pin 6: Output
  • Pin 7: V+ (Positive Supply)
  • Pin 8: NC (No Connect)

The input resistance ($R_{in}$) is measured between Pin 2 and Pin 3 (differential input resistance) or from either input pin to the internal ground/common-mode reference. When a signal source with its own output resistance ($R_s$) connects to Pin 3, $R_s$ and the op amp’s $R_{in}$ form a voltage divider. If $R_{in}$ is not at least 100 times larger than $R_s$, you will lose a measurable percentage of your signal voltage before it even enters the amplification stage.

Input Stage Technologies: Bipolar vs. JFET vs. CMOS

The input resistance is entirely dictated by the semiconductor technology used in the input differential pair. According to the Texas Instruments Precision Labs Op Amp Training Series, selecting the wrong input topology is the most common cause of unexplained DC offsets in high-impedance sensor circuits.

Op Amp Input Stage Characteristics and Operating Regions
Technology Typical Input Resistance ($R_{in}$) Input Bias Current ($I_B$) Input Offset Voltage ($V_{os}$) Typical Supply Range Best Use Case
Bipolar (BJT) 300 kΩ to 10 MΩ 10 nA to 1 µA Very Low (< 100 µV) ±5V to ±18V Low-impedance sources, precision DC, audio line drivers
JFET 1011 Ω to 1012 Ω 10 pA to 100 pA Low to Medium (1 mV - 5 mV) ±5V to ±18V Audio preamps, mid-impedance sensors, active filters
CMOS > 1012 Ω (Tera-ohms) < 1 pA (often fA range) Medium to High (1 mV - 10 mV) +2.7V to +15V (Single or Dual) Piezo sensors, pH probes, photodiode transimpedance amps
Bench Tip: Input bias current ($I_B$) is the practical manifestation of input resistance. Even if the datasheet claims infinite input resistance, a bias current of 50 nA flowing through a 1 MΩ source resistor will generate a 50 mV DC error at the input. Always calculate $V_{error} = I_B imes R_{source}$.

Decision Tree: Selecting the Right Op Amp

Do not default to the LM741 or LM358 out of habit. Use this decision matrix to pick the correct input stage based on your source impedance and noise requirements.

Op Amp Selection Decision Path
Source Impedance ($R_s$) Primary Requirement Required Technology Concrete Part Pick
< 1 kΩ (e.g., DAC outputs, low-Z mics) Lowest voltage noise, lowest $V_{os}$ drift Bipolar (BJT) OPA227 or NE5532
1 kΩ to 100 kΩ (e.g., guitar pickups, voltage dividers) Balance of low noise, high $R_{in}$, and good slew rate JFET TL072 or OPA2134
> 100 kΩ (e.g., piezo discs, pH electrodes, photodiodes) Ultra-high $R_{in}$, near-zero input bias current CMOS LMC6482 or MCP6001

Application Circuit: High-Impedance Piezo Sensor Buffer

Piezo transducers act as small capacitors (typically 10 nF to 50 nF) with massive equivalent source resistance, often exceeding 10 MΩ. If you buffer a piezo with a bipolar op amp, the input bias current will charge the piezo element, pegging the output to the positive supply rail. We must use a CMOS op amp and provide a deliberate DC bias path.

Component List and Values

  • U1: LMC6482 (Dual CMOS Op Amp, $R_{in} > 10^{12}$ Ω, $I_B = 0.02$ pA typical)
  • R1: 10 MΩ resistor (DC return path to ground)
  • C1: 100 nF film capacitor (AC coupling from piezo)
  • C2, C3: 10 µF electrolytic + 100 nF ceramic (Supply bypass caps)
  • R2: 100 Ω resistor (Output isolation to prevent capacitive load oscillation)

Wiring and Biasing Steps

  1. Power Decoupling: Connect Pin 7 (V+) to your positive supply (e.g., +9V) and Pin 4 (V-) to Ground. Place C2 (10 µF) and C3 (100 nF) directly across Pin 7 and Pin 4 as close to the IC body as possible to prevent high-frequency rail oscillation.
  2. Input Biasing (Crucial): Connect R1 (10 MΩ) between Pin 3 (Non-Inverting Input) and Ground (Pin 4). This resistor provides the necessary DC path for the ultra-low CMOS input bias current. Without R1, the input pin will float, accumulate static charge, and latch up.
  3. AC Coupling: Connect one lead of the piezo sensor to one side of C1 (100 nF). Connect the other side of C1 to Pin 3. This blocks any DC offset from the sensor while passing the AC vibration signal.
  4. Feedback Loop: For a unity-gain buffer, connect Pin 6 (Output) directly to Pin 2 (Inverting Input).
  5. Output Protection: Route the signal from Pin 6 through R2 (100 Ω) to your output jack or ADC. R2 isolates the op amp's internal compensation from the capacitance of the cable or ADC sampling capacitor, as detailed in Analog Devices' guidelines on op amp stability.

Failure Modes and Multimeter Testing

Op amp input stages are highly susceptible to Electrical Overstress (EOS) and Electrostatic Discharge (ESD). When an op amp 'fails', it rarely explodes; instead, the internal input protection diodes short out, destroying the input resistance.

How the Input Stage Fails

Most op amps feature back-to-back diodes between the input pins, and diodes from the inputs to the supply rails. If a voltage spike exceeds the supply rails by more than 0.3V, or if the differential voltage between Pin 2 and Pin 3 exceeds the datasheet limit (often ±5V), these diodes conduct. If the current isn't limited by an external resistor, the diode junction melts into a low-resistance short. Your 1 TΩ input resistance instantly becomes 50 Ω.

Testing with a Digital Multimeter (DMM)

You can diagnose a blown input stage on the bench without powering the circuit, using your DMM’s diode-test mode.

  1. De-energize and Isolate: Remove all power from the circuit. If the op amp is in-circuit, ensure the input pins aren't shunted by low-value feedback resistors (lift the pin if necessary).
  2. Test Rail Protection Diodes: Set your DMM to diode mode. Place the red probe on Pin 4 (V-) and the black probe on Pin 3 (IN+). You should read a standard silicon diode drop (0.55V to 0.75V). Reverse the probes; it should read 'OL' (Open Loop).
  3. Test Differential Inputs: Place probes across Pin 2 and Pin 3. You should read 'OL' in both directions. If you read a dead short (0.00V) or a very low resistance in both directions, the internal back-to-back protection diodes are blown. The IC is dead.
  4. Live Bias Current Test: Power the circuit. With the input grounded through a known resistor (e.g., 1 MΩ), measure the DC voltage at the input pin. According to All About Circuits semiconductor theory, $V = I_B imes R$. If you measure 50 mV across a 1 MΩ resistor, your bias current is 50 nA. If you measure 2V, your input stage has suffered leakage damage and is pulling massive current.
Safety & Handling Warning: CMOS op amps (like the LMC6482) have gate oxides that are only a few nanometers thick. Always use a grounded wrist strap and ESD-safe mat when handling them. Never insert or remove a CMOS op amp from a breadboard while the power is on; the floating pins can induce latch-up, permanently shorting V+ to Ground inside the silicon.

The 'Safe Defaults' Cheat Sheet

When prototyping or when the exact source impedance is unverified, do not guess. Rely on these three benchmark part numbers that cover 95% of bench and production needs. These are the concrete defaults you should stock in your lab.

  • The Audio & General Purpose Default: TL072 (JFET)
    • Ratings: $R_{in} = 10^{12}$ Ω, $I_B = 50$ pA, Slew Rate = 13 V/µs, Supply = ±18V max.
    • Why: It offers JFET-level input impedance with excellent audio-band noise performance. It won't load down guitar pickups or high-Z voltage dividers. Approximate cost: $0.50 per unit.
  • The Precision DC Default: OPA227 (Bipolar)
    • Ratings: $R_{in} = 200$ MΩ, $I_B = 1$ nA, $V_{os} = 25$ µV max, Supply = ±18V max.
    • Why: When reading low-impedance RTDs, strain gauges, or DAC outputs, JFET noise is too high. The OPA227’s bipolar input provides microvolt-level precision. Approximate cost: $3.50 per unit.
  • The Ultra-High Impedance Default: LMC6482 (CMOS)
    • Ratings: $R_{in} > 10^{12}$ Ω, $I_B = 0.02$ pA, Supply = 3V to 15V (Single or Dual).
    • Why: The undisputed king of electrometer-grade buffering. Essential for pH probes, piezo films, and sample-and-hold circuits where even picoamps of bias current cause unacceptable droop. Approximate cost: $1.20 per unit.

By matching your source impedance to the correct input topology and providing a deliberate DC bias path, you eliminate the loading errors and floating-pin latch-ups that plague poorly designed analog front ends. Stock the TL072, OPA227, and LMC6482, and you will have the right input resistance for any signal you encounter.