An op amp based integrator outputs a voltage proportional to the time-integral of its input voltage. The core transfer function is Vout = -1/(RC) ∫ Vin dt. While textbooks treat this as a pure mathematical block, on the workbench, an integrator is a capacitor that slowly accumulates charge, and your primary job as a designer is to manage the inevitable leakage, bias currents, and DC offsets that threaten to rail the output. This guide bridges the gap between ideal theory and practical circuit implementation.

The Anatomy of an Op Amp Based Integrator

The standard inverting integrator relies on the op amp's virtual ground to force a constant current through the input resistor, which then charges the feedback capacitor.

Symbol and Pinout Mapping:
In a standard 8-pin DIP or SOIC package (using the ubiquitous pinout shared by 95% of dual/single op amps), the circuit maps as follows:

  • Pin 2 (Inverting Input, IN-): The summing node. Connects to the input resistor (Rin) and the feedback capacitor (Cf). This is the virtual ground.
  • Pin 3 (Non-Inverting Input, IN+): Connects to ground (0V) or a precise DC reference voltage if you need to integrate around a non-zero baseline.
  • Pin 6 (Output, OUT): The other side of the feedback capacitor. The voltage here moves to whatever level is required to keep Pin 2 at the same potential as Pin 3.
  • Pins 7 (V+) and 4 (V-): Power supply rails. For precision integration, symmetric rails (e.g., ±15V or ±5V) are preferred to keep the output swing centered and avoid common-mode input range violations.

Selecting the Right Op Amp and Biasing the Network

The silent killer of integrator circuits is input bias current (Ib). Even with the input grounded, the op amp's internal transistors draw a tiny current from the summing node. This current has nowhere to go but into the feedback capacitor, causing the output to ramp up or down until it hits the supply rail.

Safe Default Part Numbers

Do not use a legacy LM741 or standard LM358 for precision integration; their bipolar input stages have bias currents in the nanoamp range, which will charge a 100nF capacitor at a rate of several volts per second. Choose based on your integration time constant:

  • OPA2188 (Texas Instruments): A chopper-stabilized, zero-drift op amp. Ib is typically ±250 pA, and input offset voltage (Vos) is practically zero (25 μV max). This is the ultimate safe default for DC-coupled, long-duration integration.
  • LMC6062 (Texas Instruments): A precision CMOS dual op amp. Ib is an astonishing 10 fA. Use this when integrating with large capacitors (1 μF or higher) where even picoamps of bias current cause drift.
  • TL072 (Texas Instruments): A JFET-input op amp. Higher bias current than CMOS, but exceptionally low voltage noise. Choose this for audio-frequency integration or fast PID control loops where integration times are under 10 milliseconds.

Biasing and the DC Stabilization Resistor

To prevent DC offsets from railing the output, you must add a high-value feedback resistor (Rf) in parallel with Cf. This creates a low-frequency pole, turning the pure integrator into a low-pass filter at DC. Rule of thumb: set Rf to be at least 10× larger than Rin. If Rin is 10 kΩ, use a 1 MΩ or 10 MΩ resistor for Rf.

Operation Regions and Practical Component Values

Below is a complete application circuit for a precision square-to-triangle wave converter with a MOSFET reset switch. This is a common topology in function generators and PID controllers.

Circuit Values:

  • U1: OPA2188 (Single supply ±12V)
  • Rin: 10 kΩ (1% metal film)
  • Cf: 100 nF (Polypropylene or C0G/NP0 ceramic)
  • Rf: 1 MΩ (DC stabilization)
  • Reset Switch: 2N7000 N-channel MOSFET placed in parallel with Cf, driven by a microcontroller GPIO to discharge the cap and reset Vout to 0V.
Op Amp Integrator Operation Regions (±12V Supply)
Region State Description Typical Voltages / Currents Virtual Ground Status
Linear Integration Cf is charging/discharging linearly. Output ramps within supply limits. Vout = -10V to +10V
Ic = Vin / Rin		 Holds tightly (Pin 2 ≈ 0V)
Saturation (Railed) Output hits the internal transistor limits. Integration stops; capacitor holds max charge. Vout = ±11.2V (approx)
Ic drops to near zero		 Lost (Pin 2 diverges from Pin 3)
Reset / Dump MOSFET across Cf turns on. Capacitor rapidly discharges through the FET's RDS(on). Vout snaps to 0V
Ipeak limited by MOSFET		 Transient disruption, then recovers
Bench Tip: Avoid X7R and Y5V Capacitors
Never use high-K dielectric ceramics (X7R, X5R, Y5V) for Cf. These materials exhibit severe dielectric absorption (the capacitor "remembers" previous voltages and leaks them back into the circuit) and are piezoelectric (they act as microphones, injecting noise when vibrated). Always specify C0G/NP0 ceramic or polypropylene film capacitors for the feedback loop. For a deep dive on passive component quirks, reference the All About Circuits integrator guide.

Bench Walkthrough: When the Output Rails to VCC

Let's walk through a classic bench failure to see how the math translates to real-world debugging.

The Setup: You are building an integrator to convert a 50 Hz, 100 mV amplitude square wave from a function generator into a triangle wave. You use the circuit values above: Rin = 10 kΩ, Cf = 100 nF. You omitted Rf because you wanted a "pure" integrator.

The Numbers:
The ideal integration slope is dV/dt = -Vin / (Rin × Cf).
With Vin = 100 mV (0.1 V), the slope is -0.1 / (10,000 × 0.0000001) = -100 V/s.
Since a 50 Hz square wave has a 10 ms (0.01 s) half-cycle, the output should ramp by exactly ΔV = -100 V/s × 0.01 s = -1.0 V per half-cycle. You expect a beautiful 2V peak-to-peak triangle wave.

The Outcome:
You hook up the oscilloscope. The triangle wave looks perfect for about two seconds. Then, the entire waveform slowly drifts downward on the screen until it flatlines at -11.2V (the negative saturation rail).

What Went Wrong:
Your function generator had a tiny, uncalibrated DC offset of +5 mV. The op amp didn't just integrate the 100 mV AC square wave; it faithfully integrated the 5 mV DC offset as well.
The error slope was -0.005 / 0.001 = -5 V/s.
Over 2 seconds, this accumulated to -10V of DC drift, pushing the output into saturation. Furthermore, the OPA2188's own input offset voltage and bias current added micro-volts of additional drift. Without a parallel Rf to bleed off this DC error, a pure integrator will always eventually rail in the presence of real-world DC offsets.

The Fix:
Add a 1 MΩ resistor in parallel with the 100 nF capacitor. This creates a high-pass cutoff frequency for the error signal at fc = 1 / (2π × 1MΩ × 100nF) ≈ 1.59 Hz. Because your signal is 50 Hz, the integrator handles it perfectly, but the 0 Hz DC offset is shunted through the resistor, stabilizing the output baseline. For more on handling op amp offsets, consult the Electronics Tutorials op amp integrator reference.

Troubleshooting and Multimeter Testing Guide

When your integrator is misbehaving on the bench, put the oscilloscope aside for a moment and grab your digital multimeter (DMM). Here is a systematic decision path to isolate the fault.

  1. Verify the Virtual Ground (Power ON):
    Set your DMM to the millivolt DC range. Place the black probe on Pin 3 (Non-Inverting/Ground) and the red probe on Pin 2 (Inverting).
    Pass: Reading is < 2 mV. The op amp is in its linear region and the feedback loop is intact.
    Fail: Reading is > 50 mV. The op amp has lost virtual ground, meaning the output is railed, the feedback capacitor is open, or the IC is damaged.
  2. Check the DC Stabilization Path (Power OFF):
    Disconnect power. Set the DMM to resistance (Ω). Measure between Pin 6 (Output) and Pin 2 (Inverting).
    Pass: You should read the value of your Rf resistor (e.g., 1 MΩ).
    Fail: If it reads OL (Open Loop), your Rf is broken or unsoldered, guaranteeing DC drift. If it reads near 0 Ω, your feedback capacitor has failed short.
  3. Test for Capacitor Dielectric Absorption (Component Level):
    If the circuit works but the reset function leaves a "ghost" voltage that slowly creeps back, your capacitor is suffering from dielectric absorption. Desolder Cf, charge it to 5V with a bench supply for 10 seconds, short it with a wire for 1 second, then remove the short and measure the voltage with your DMM. A good C0G or film cap will read 0.000V. An X7R ceramic might "recover" to 50 mV or more, ruining precision integration.
  4. Verify Output Swing Limits (Power ON):
    Force a known DC voltage into the input (e.g., 1V) and measure Pin 6. Ensure the output is moving toward the opposite rail but stops roughly 0.8V to 1.5V short of the actual VCC/VEE pins, depending on the op amp's output stage specifications. If it hits the exact rail voltage, you may be dealing with a non-rail-to-rail output stage clipping the signal.

Building an op amp based integrator is a masterclass in managing non-ideal component behaviors. By selecting a low-bias-current IC like the OPA2188, specifying a C0G or polypropylene capacitor, and properly sizing your DC stabilization resistor, you transform a fragile textbook equation into a robust, bench-proven circuit block.