The NOT logic gate truth table defines a single-input, single-output inverter where the output is the exact logical complement of the input. In Boolean algebra, this is expressed as Y = A' or Y = ¬A. However, on the workbench, a basic 1-and-0 truth table is practically useless without the voltage thresholds that define what your specific logic family considers a '0' or a '1'. Interfacing a 3.3V ESP32 GPIO to a 5V 74HC04 inverter without checking the datasheet thresholds is a classic way to end up with floating logic and erratic behavior.
This reference guide provides the complete NOT gate truth table alongside the critical JEDEC and manufacturer voltage specifications, derating curves, and edge cases for standard TTL and CMOS logic families.
The Core NOT Logic Gate Truth Table & Symbol
At the abstract digital level, the NOT gate (inverter) operates on a simple binary inversion. The standard ANSI/IEEE symbol is a triangle with a bubble at the output.
| Input (A) | Output (Y) | Boolean Expression | Common IC Part Numbers |
|---|---|---|---|
| 0 (LOW) | 1 (HIGH) | Y = A' / Y = ¬A | 7404 (TTL), 74LS04 (Schottky), 74HC04 (CMOS), CD4069 (4000-series CMOS) |
| 1 (HIGH) | 0 (LOW) |
Logic Family Voltage Thresholds (How to Read the Spec Table)
The physical reality of a logic '1' or '0' depends entirely on your supply voltage (VCC) and the semiconductor technology inside the IC. The table below is compiled from Texas Instruments SN74HC04 datasheets and the JEDEC JESD8C standard for 3V/5V logic interfaces.
Bookmark Quick-Jump: [5V TTL Thresholds] | [5V CMOS Thresholds] | [3.3V CMOS Thresholds]
| Logic Family | VCC (Nominal) | VIL (Max) | VIH (Min) | VOL (Max) | VOH (Min) | Standard |
|---|---|---|---|---|---|---|
| 74LS (TTL) | 5.0V | 0.8V | 2.0V | 0.4V | 2.7V | JEDEC JESD8C |
| 74HC (CMOS) | 5.0V (4.5V min) | 1.35V (at 4.5V) | 3.15V (at 4.5V) | 0.1V | 4.4V | JEDEC JESD8C |
| 74HC (CMOS) | 3.3V (3.0V min) | 0.9V (at 3.0V) | 2.1V (at 3.0V) | 0.1V | 2.9V | JEDEC JESD8C |
| 74HCT (CMOS w/ TTL inputs) | 5.0V | 0.8V | 2.0V | 0.1V | 4.4V | JEDEC JESD8C |
| CD4069 (4000-series) | 5.0V to 15V | 1.5V (at 5V) | 3.5V (at 5V) | 0.05V | 4.95V | Manufacturer Spec |
Which Column Applies to Your Installation?
If you are wiring a 5V Arduino Uno to a 74HC04, use the 5V CMOS row. The Arduino's ATmega328P outputs a VOH of roughly 4.5V, which easily clears the 74HC04's 3.15V VIH requirement. However, if you are wiring a 3.3V Raspberry Pi or ESP32 to a 5V 74HC04, the 5V CMOS row reveals a fatal flaw: the ESP32's maximum 3.3V output falls dangerously close to (or below, under load) the 74HC04's 3.15V minimum VIH. In this scenario, you must switch to a 74HCT04, which uses CMOS output rails but features TTL-compatible input thresholds (accepting 2.0V as a solid HIGH).
Fan-Out, Loading, and Propagation Delay Derating
The base propagation delay (tpd) listed in a NOT gate truth table or summary spec sheet is typically measured under ideal bench conditions: a 25°C ambient temperature and a standard 50pF capacitive load. In a real PCB layout, these rows modify the base value significantly.
- Capacitive Loading (Fan-Out): Every logic gate input you wire to the NOT gate's output adds roughly 10pF to 15pF of parasitic capacitance. Long breadboard jumper wires can add 2pF per inch. For a 74HC04, every additional 50pF of load capacitance derates the propagation delay by approximately 12ns to 15ns. If you are driving a heavy capacitive load (like a long coaxial cable or a power MOSFET gate), the delay increases, and the rise/fall times stretch, increasing the risk of shoot-through current.
- Temperature Derating: Silicon slows down as it gets hotter. At the industrial limit of 85°C, the VIH threshold drops slightly and the VIL threshold rises, shrinking your noise margin. More critically, the propagation delay increases by roughly 15% to 20% compared to the 25°C baseline. If you are designing a high-speed clock oscillator using cascaded NOT gates, a 50MHz circuit at room temperature might fail to oscillate at 60°C due to this thermal derating.
What the Truth Table Cannot Tell You (Edge Cases)
A static 1-and-0 truth table hides the dynamic, analog realities of semiconductor physics. Here is what the basic chart omits:
Unlike older 74LS TTL gates, which have internal pull-up resistors that cause unconnected inputs to default to a logical HIGH, CMOS gates (74HC, CD4000) have near-infinite input impedance. If you leave a NOT gate input floating, it acts as a high-gain antenna. It will pick up 60Hz mains hum, RF noise, and static. The gate will rapidly oscillate between HIGH and LOW. During this transition, both the internal P-channel and N-channel MOSFETs turn on simultaneously, creating a low-resistance path from VCC to GND. This 'shoot-through' current will cause the IC to overheat and potentially melt the silicon die. Always tie unused CMOS inputs to VCC or GND.
Furthermore, the truth table assumes instantaneous transitions. In reality, a NOT gate spends a few nanoseconds in the linear region during switching. If you feed a slow-moving analog signal (like a triangle wave) into a 74HC04, the output will not be a clean square wave; it will exhibit ringing and multiple false triggers due to the lack of internal Schmitt-trigger hysteresis. For noisy or slow signals, you must use a Schmitt-trigger inverter like the 74HC14.
Frequently Asked Questions (FAQ)
Can I use a 74HC04 NOT gate to level-shift a 3.3V signal to 5V?
No, not reliably. While the 74HC04 can be powered by 5V and will output a 5V HIGH signal, its input threshold (VIH) at 5V is 3.15V. A 3.3V microcontroller GPIO might only output 3.1V under slight load, leaving the 74HC04 in the undefined region. To level-shift 3.3V logic to 5V using a NOT gate, use a 74HCT04 (which accepts TTL-level 2.0V inputs) or a dedicated level-shifter like the TXB0104.
Why does my CD4069 NOT gate output a square wave when nothing is connected?
You are witnessing the floating input effect combined with parasitic feedback. The CD4069 has massive internal gain. A floating pin picks up ambient electromagnetic interference, causing the gate to act as a linear amplifier rather than a digital switch. If there is even a fraction of a picofarad of stray capacitance coupling the output trace back to the input trace on your breadboard, the gate will form an astable multivibrator (oscillator) and output a high-frequency square wave. Tie the input to GND with a 10kΩ resistor to stop it.
What is the difference between a NOT gate and a buffer in physical wiring?
Logically, a buffer (like the 74HC125) just passes the signal through (Y = A), while a NOT gate inverts it (Y = A'). Physically, the difference is drive strength. A standard 74HC04 NOT gate can typically source or sink about 4mA to 6mA. A dedicated buffer IC is designed with massive output transistors capable of sourcing 25mA to 35mA, allowing it to directly drive LEDs, small relays, or heavily loaded bus lines without sagging the voltage below the VOH threshold.
How do I calculate the power dissipation of a 74LS04 hex inverter?
Power dissipation in a logic gate has two components: quiescent (static) and dynamic (switching). For a 74LS04, the quiescent current (ICC) is roughly 1.2mA per gate when the output is HIGH, and 3.6mA when LOW. At 5V, static power is roughly P = V × I. However, dynamic power dominates at high frequencies. Every time the gate switches, it charges and discharges the load capacitance. The formula is Pdynamic = CL × VCC² × f, where f is the switching frequency. If you are running a 74LS04 at 20MHz with a 50pF load, the dynamic power dissipation will far exceed the static draw, requiring you to check the IC's maximum junction temperature limits.
