A half-bridge circuit switches a load between a high and low voltage rail using two series-connected switches. If you need to drive a 24V, 10A load with bidirectional current flow—such as a thermoelectric cooler (TEC), a center-tapped transformer, or an AC-coupled resonant tank—without the gate-drive complexity of four switches, the default pick is a pair of IRF3205 N-channel MOSFETs driven by an IR2104 half-bridge gate driver. This configuration delivers the necessary voltage swing while minimizing board space and bootstrap component count.

The Half-Bridge Topology & Node Labels

To read or draw a half bridge circuit diagram correctly, you must map the four critical nodes. Unlike a simple low-side switch, the half-bridge creates a floating switch node that requires specialized gate driving.

  • V_BUS (Positive DC Rail): The main supply voltage (e.g., +24V). Connects to the drain of the high-side MOSFET (Q1) and the top of the split DC bus capacitor bank.
  • SW (Switch Node): The midpoint between the source of Q1 and the drain of the low-side MOSFET (Q2). This node swings from 0V to V_BUS and connects to one terminal of your load.
  • PGND (Power Ground): The 0V reference. Connects to the source of Q2 and the bottom of the split capacitor bank.
  • V_MID (Capacitor Midpoint): The junction between the two series DC bus capacitors (C_BUS1 and C_BUS2). For AC loads, the second load terminal connects here to provide a virtual ground and a path for alternating current.
Bench Tip: If your load is purely DC and grounded (like a synchronous buck converter inductor), you do not need the split capacitor bank or the V_MID node. The load simply connects between the SW node and PGND. The split capacitors are only mandatory when the load requires an AC return path referenced to half the bus voltage.

Decision Path: Half-Bridge vs. Full-Bridge

Choosing between a half-bridge and a full-bridge (H-bridge) dictates your entire gate-drive architecture and component budget. Use the decision matrix below to terminate your design choice.

Design Requirement Half-Bridge Full-Bridge (H-Bridge)
Switch Count 2 MOSFETs 4 MOSFETs
Output Voltage Swing ±(V_BUS / 2) ±V_BUS
Gate Drive Complexity 1 High-side, 1 Low-side 2 High-side, 2 Low-side
DC Bus Requirement Requires split capacitor bank for AC loads Single DC bus capacitor

The Decision Tree

  • IF your load requires a full ±V_BUS swing across a grounded or floating load (e.g., reversing a 24V DC motor) → Choose a Full-Bridge.
  • IF your load is AC-coupled, center-tapped, or requires only ±(V_BUS/2) and you want to halve your gate-driver IC count → Choose a Half-Bridge.
  • DEFAULT PICK: For a 24V inverter or TEC driver where component count and thermal management are prioritized over maximum voltage swing, build the Half-Bridge using the IR2104 and IRF3205.

Behavior & Failure Modes at the Extremes

A half-bridge is unforgiving of timing errors. Because Q1 and Q2 share the same SW node, any overlap in their conduction states creates a direct short across V_BUS and PGND. This is known as shoot-through, and it will instantly vaporize silicon and copper traces. According to Infineon's gate driver design guidelines, implementing hardware dead-time is non-negotiable.

Here is exactly what breaks when components fail or timing slips:

Fault Condition Circuit Behavior Physical Result
Q1 (High) Short-Circuit V_BUS is permanently tied to the SW node. If Q2 turns on, a dead short occurs. Catastrophic shoot-through; Q2 explodes, PCB traces lift.
Q2 (Low) Open-Circuit SW node loses its path to PGND. Inductive loads will force the SW node negative. SW node rings below ground; Q1 body diode conducts, potentially overheating.
Gate Drive Loss (Both Off) Inductive load current has no active freewheeling path. SW node voltage spikes until MOSFETs hit avalanche breakdown (V_DSS), usually destroying them.
Insufficient Dead-Time Q1 and Q2 are partially ON simultaneously during transitions. High-frequency current spikes, severe EMI, and thermal runaway in the MOSFETs.

Design Walkthrough: 24V 10A Half-Bridge

Let’s assign real component values for a 24V, 10A continuous half-bridge. We are using the classic half-bridge inverter topology adapted for a DC/AC load.

1. The Power Stage (MOSFETs)

Select the IRF3205. It is rated for 55V (giving a >2x safety margin over 24V) and features an R_DS(on) of 8mΩ. At 10A, conduction loss per FET is I²R = 100 * 0.008 = 0.8W, which is easily managed with a small TO-220 heatsink or adequate PCB copper pour.

2. The Gate Driver & Bootstrap Network

The IR2104 is ideal because it features built-in dead-time generation (typically 520ns) and a single input pin for PWM, preventing software-induced shoot-through.

  • Bootstrap Diode (D_BOOT): Use a UF4007 (1A, 1000V, ultra-fast recovery). A standard 1N4007 is too slow and will allow V_BUS to bleed back into the VCC rail during the SW node rise.
  • Bootstrap Capacitor (C_BOOT): Must supply the high-side gate charge. The IRF3205 total gate charge (Q_g) is ~120nC. Using the formula C_BOOT ≥ Q_g / ΔV_BOOT (assuming a 1V allowable droop), we need 120nF minimum. We select a 1µF X7R ceramic capacitor placed as physically close to the VB and VS pins as possible to minimize trace inductance.

3. Gate Resistors (R_G)

Do not connect the driver outputs directly to the gates. Use a split gate resistor network to control di/dt and dampen ringing:

  • Turn-on resistor: 10Ω (limits inrush current into the gate capacitance, protecting the IR2104).
  • Turn-off resistor: 4.7Ω (faster turn-off to minimize switching losses and shrink the dead-time vulnerability window).
  • Schottky Diode: A BAT54S placed in parallel with the turn-on resistor (cathode to driver, anode to gate) to bypass the 10Ω resistor during turn-off.

4. The DC Bus Capacitors

For a 10A load, the split capacitors (C_BUS1 and C_BUS2) must handle the RMS ripple current. Use two 1000µF 50V low-ESR electrolytic capacitors in series, bypassed by two 100nF 50V X7R ceramics placed directly across the drain and source of each MOSFET to absorb high-frequency switching spikes.

Breadboard Testing Protocol

Never apply V_BUS to an untested half-bridge. Follow this exact sequence to verify the circuit without risking a short circuit.

  1. DMM Diode Check: With power disconnected, use your multimeter’s diode mode. Probe Q1 (Source to Drain) and Q2 (Source to Drain). You should read ~0.4V (the body diode drop). If you read 0.0V, a MOSFET is already shorted. Discard and replace.
  2. Logic Power Up: Apply 12V to the IR2104 VCC pin and GND. Do not connect V_BUS yet. Measure the voltage between the HO (High-side Output) and VS pins with an oscilloscope while injecting a 10kHz PWM signal into the IN pin. You must see a clean 12V square wave referenced to VS.
  3. Bootstrap Verification: Measure the voltage between VB and VS. It should read approximately VCC minus one diode drop (~11.3V). If it reads 0V, your UF4007 diode is backward or C_BOOT is missing.
  4. Low-Side Verification: Measure LO to PGND. You should see an inverted, dead-time-shifted version of your input PWM signal, swinging from 0V to 12V.
  5. Controlled Bus Application: Connect V_BUS through a bench power supply set to a strict 1A current limit. Apply 24V. Monitor the supply current. With no load connected, the quiescent current should be under 20mA. If the supply hits the 1A limit and the voltage collapses, you have shoot-through or a wiring fault.
  6. SW Node Snubber Check: Connect a 10:1 oscilloscope probe to the SW node (ensure your scope is isolated or use a differential probe if the load ground is not earth-referenced). Look for ringing exceeding 35V. If present, add a 10Ω + 1nF RC snubber directly across the SW node and PGND.

By strictly adhering to this component selection and testing sequence, your half bridge circuit diagram transitions from a theoretical schematic to a robust, fault-tolerant power stage capable of handling real-world inductive and AC loads.