A NOR gate outputs a logical HIGH (1) only when all of its inputs are LOW (0). If any single input goes HIGH, the output immediately pulls LOW. Because it can be combined to replicate any other Boolean function, the NOR gate is classified as a "universal gate" in digital logic design. But a static Boolean table only gets you halfway through a real-world build. To actually wire one up, you need to know the voltage thresholds, propagation delays, and exact part numbers for your specific logic family.
The Standard NOR Logic Gate Truth Table (ANSI/IEEE Std 91-1984)
Below is the complete 2-input NOR logic gate truth table, formatted per ANSI/IEEE Std 91-1984 graphic symbols and logic conventions.
How to read this table: The first two columns represent your digital inputs (A and B). The third column is the idealized Boolean output (Y). The final column is what your multimeter will actually read on the output pin if you are using a standard 5V CMOS chip (like the 74HC02) under a 2mA load. Bookmark the first row—that is the only state that yields a HIGH output.
| Input A (Logic) | Input B (Logic) | Output Y (Logic) | Output Y (5V HC CMOS Voltage) |
|---|---|---|---|
| 0 (LOW) | 0 (LOW) | 1 (HIGH) | ~4.9V (Min guaranteed: 4.4V) |
| 0 (LOW) | 1 (HIGH) | 0 (LOW) | ~0.1V (Max guaranteed: 0.33V) |
| 1 (HIGH) | 0 (LOW) | 0 (LOW) | ~0.1V (Max guaranteed: 0.33V) |
| 1 (HIGH) | 1 (HIGH) | 0 (LOW) | ~0.1V (Max guaranteed: 0.33V) |
What the Truth Table Cannot Tell You
A truth table is a static, idealized snapshot. It assumes infinite time and perfect signals. In practice, it completely hides three critical physical realities:
- Propagation Delay ($t_{pd}$): When inputs change, the output does not flip instantly. For a Texas Instruments SN74HC02 running at 5V, the typical propagation delay is 14 nanoseconds. At 2V, that stretches to 55ns. If you are clocking signals above 20MHz, this delay creates phase shifts that a truth table will never warn you about.
- The Analog "Forbidden Zone": Digital logic is just analog circuitry pushed to its extremes. Between the maximum LOW input voltage ($V_{IL}$, typically 1.35V) and the minimum HIGH input voltage ($V_{IH}$, typically 3.15V), the gate enters a linear transition region. If an input lingers in this 1.8V-wide gap, the output becomes unpredictable, and the internal transistors draw massive amounts of shoot-through current, overheating the chip.
- Metastability: If Input A goes HIGH and Input B goes LOW at the exact same picosecond, the internal SR-latch structures of the gate can enter a metastable state, oscillating or hanging at half-rail voltage before eventually resolving.
Logic Families: Which Voltage Column Applies to Your Circuit?
The 5V CMOS voltages in the table above only apply if you are using the 74HC (High-speed CMOS) family. If you are interfacing with older TTL or modern 3.3V microcontrollers, the voltage column changes entirely. Here is how to map the logic states to your specific hardware:
| Logic Family | Typical Part | $V_{CC}$ Range | LOW Threshold ($V_{IL}$ Max) | HIGH Threshold ($V_{IH}$ Min) |
|---|---|---|---|---|
| 74HC (CMOS) | 74HC02 | 2.0V - 6.0V | 1.35V (at 4.5V $V_{CC}$) | 3.15V (at 4.5V $V_{CC}$) |
| 74LS (TTL) | 74LS02 | 4.75V - 5.25V | 0.8V | 2.0V |
| 74LVC (Low Voltage) | 74LVC02 | 1.2V - 3.6V | 0.8V (at 2.7V $V_{CC}$) | 2.0V (at 2.7V $V_{CC}$) |
| CD4000 (Classic CMOS) | CD4001B | 3.0V - 15.0V | 1.5V (at 5V $V_{CC}$) | 3.5V (at 5V $V_{CC}$) |
Design Rule: Never drive a 74HC input directly from a 3.3V ESP32 or Raspberry Pi GPIO. The 3.3V HIGH output falls short of the 74HC's 3.15V minimum requirement, leaving you with only a 0.15V noise margin. Use a 74LVC02 instead, which guarantees a HIGH threshold well below 3.3V.
Fan-Out Loading: How Signal Degradation Modifies the Base Value
In wire sizing, we derate ampacity based on heat. In logic gates, we "derate" based on fan-out—the number of inputs a single output can reliably drive. The truth table assumes an ideal, unloaded output. In reality, every input you connect draws a tiny amount of leakage current, and the output transistor has internal resistance ($R_{DS(on)}$).
If you connect the output of one 74HC02 gate to the inputs of ten other gates, the output voltage will sag.
- Source Current ($I_{OH}$): When outputting HIGH, the chip sources current. If you exceed the rated 4mA limit, the $V_{OH}$ drops below the 4.4V guaranteed minimum, potentially falling into the forbidden zone for the next gate in the chain.
- Sink Current ($I_{OL}$): When outputting LOW, the chip sinks current to ground. Exceeding 4mA causes the $V_{OL}$ to rise above 0.33V, which a sensitive TTL input might misinterpret as a HIGH.
The Fix: A standard 74HC output can safely drive up to 10 LS-TTL inputs or 20 HC-CMOS inputs. If your design requires driving more (like a large LED matrix or a long bus), buffer the NOR gate output with a dedicated driver like the ULN2003 or a 74HC244 octal buffer.
Decision Tree: Picking Your Exact NOR Gate Part Number
Stop guessing which IC to order. Follow this decision path to select the exact NOR gate part number for your build.
| If your project requires... | Then choose this Logic Family... | Order this Exact Part Number (DIP-14) |
|---|---|---|
| Standard 5V breadboard prototyping, moderate speed | 74HC (High-Speed CMOS) | SN74HC02N (Texas Instruments) |
| Interfacing 3.3V microcontrollers (ESP32, Pi Pico) to 5V systems | 74LVC (Low-Voltage CMOS, 5V tolerant inputs) | 74LVC02AP (NXP / Diodes Inc) |
| Battery-powered, wide-voltage (9V/12V) analog synthesis or slow logic | CD4000B (Classic CMOS) | CD4001BE (Note: CD4001 is the 4000-series NOR equivalent) |
| Legacy repair, replacing old bipolar TTL boards from the 1980s | 74LS (Low-Power Schottky) | SN74LS02N (Texas Instruments) |
