An NMOS amplifier uses an N-channel Metal-Oxide-Semiconductor Field-Effect Transistor to control a larger output current via a smaller input voltage, providing signal gain. In a real circuit, it changes a high-impedance, low-current voltage signal into a lower-impedance, higher-current or higher-voltage swing signal capable of driving subsequent stages. If you are designing a sensor interface or an audio preamp, understanding how to bias and stabilize this topology is the difference between a clean signal and a clipped, oscillating mess.
The Core Mechanics: Voltage Control and Transconductance
Unlike bipolar junction transistors (BJTs) that require base current to operate, the NMOS transistor is strictly voltage-controlled. The gate draws virtually zero DC current (limited only by leakage in the nanoamp range). The amplification magic happens via transconductance ($g_m$), which defines how much the drain current ($I_D$) changes for a given change in gate-to-source voltage ($V_{GS}$).
Let us run a concrete numeric example using the ubiquitous 2N7000 N-channel enhancement MOSFET (costing roughly $0.10 per unit in bulk). We want to build a common-source amplifier with a 12V supply ($V_{DD}$) and target a mid-rail drain-to-source voltage ($V_{DS}$) of 6V to maximize symmetrical output swing.
- Calculate Drain Current ($I_D$): Using Ohm's law across the drain resistor: $I_D = (12V - 6V) / 2200\Omega = 2.72 mA$.
- Determine Gate Voltage ($V_{GS}$): The 2N7000 has a typical threshold voltage ($V_{GS(th)}$) of 2.0V and a transconductance parameter ($K_n$) of roughly $0.12 A/V^2$. Using the saturation equation $I_D = K_n(V_{GS} - V_{th})^2$, we solve for $V_{GS}$: $0.00272 = 0.12(V_{GS} - 2.0)^2$. This yields a required $V_{GS}$ of approximately 2.15V.
- Calculate Transconductance ($g_m$): $g_m = 2 \times \sqrt{K_n \times I_D} = 2 \times \sqrt{0.12 \times 0.00272} \approx 0.036 S$ (or 36 mS).
- Calculate Voltage Gain ($A_v$): $A_v = -g_m \times R_D = -0.036 \times 2200 = \mathbf{-79.2}$. The negative sign indicates a 180-degree phase inversion.
To set that 2.15V at the gate, you would use a high-impedance voltage divider from the 12V rail (e.g., $R_1 = 4.7 M\Omega$, $R_2 = 1 M\Omega$), ensuring the input signal is AC-coupled via a 1µF capacitor.
Where You Meet NMOS Amplifiers in Practice
You will rarely see a discrete NMOS amplifier driving a speaker directly. Instead, they dominate specific niches where their high input impedance and low noise floor are critical:
- Piezoelectric Sensor Conditioning: Piezo discs generate high-voltage, near-zero-current signals. An NMOS common-drain (source follower) stage buffers this high-impedance source without loading it down, passing the signal to an ADC.
- RF Front-Ends: In GHz-frequency designs, NMOS transistors (often in cascode configurations) are preferred over PMOS because electron mobility is roughly 2.5 times higher than hole mobility, allowing for higher transition frequencies ($f_T$) on the same silicon die.
- Electret Microphone Preamps: The tiny JFETs or NMOS devices inside electret mic capsules act as impedance converters, turning the capsule's capacitive output into a usable voltage signal for long cable runs.
Common Confusions: NMOS vs. PMOS, BJT, and Op-Amps
When reading schematics or selecting parts, builders frequently mix up these device classes. Here is how to separate them:
NMOS vs. PMOS: NMOS devices sink current to ground and are placed on the "low side" of a load. PMOS devices source current from the positive rail and sit on the "high side." In amplifier design, NMOS is the default for discrete small-signal stages due to better high-frequency performance and lower on-resistance ($R_{DS(on)}$) for a given die size. For a deep dive into MOSFET fundamentals, All About Circuits provides an excellent breakdown of carrier mobility differences.
MOSFET vs. BJT (e.g., 2N3904): A BJT requires continuous base current to maintain collector current (current-controlled). A MOSFET requires only voltage to charge the gate capacitance (voltage-controlled). If your signal source has an output impedance above 10kΩ, a BJT will load it down and kill your signal amplitude; an NMOS will not.
Discrete NMOS vs. Integrated Op-Amp: An op-amp (like the TL072) is essentially a complex, internally compensated network of NMOS/PMOS/BJT stages. Use an op-amp when you need precise, predictable gain set by two resistors. Use a discrete NMOS stage when you need ultra-low noise at the very first stage of amplification, or when operating at RF frequencies where standard op-amps roll off.
Decision Tree: Selecting the Right Amplifier Topology
Do not default to a complex IC when a single transistor will do, and do not force a discrete transistor when an op-amp is cheaper and more stable. Use this decision matrix to terminate your part selection:
| Signal Source / Requirement | Frequency Range | Input Impedance Need | Recommended Topology & Part |
|---|---|---|---|
| Piezo sensor, high-Z capacitor mic | DC to 20 kHz | > 1 MΩ | NMOS Source Follower (2N7000 or J310) |
| Low-Z dynamic mic, line-level audio | 20 Hz to 20 kHz | 1 kΩ to 10 kΩ | Low-Noise Op-Amp (NE5532 or OPA1612) |
| RF antenna tap, VHF/UHF mixing | 30 MHz to 500 MHz | 50 Ω to 300 Ω | NMOS Common-Gate / Cascode (BF998 or MGF1302) |
| General bench prototyping, learning | DC to 1 MHz | 100 kΩ to 10 MΩ | NMOS Common-Source (2N7000) |
Practical Build: Biasing a 2N7000 Common-Source Stage
Theoretical math is clean; the workbench is not. The primary failure mode of discrete NMOS amplifiers is thermal drift and threshold variance. The $V_{GS(th)}$ of a 2N7000 can range from 0.8V to 3.0V depending on the specific manufacturing batch and temperature. If you use a fixed voltage divider without feedback, half your boards will clip the positive rail and the other half will clip the negative rail.
Here is the professional method to stabilize the bias point using source degeneration:
- Add a Source Resistor ($R_S$): Place a 470Ω resistor between the NMOS source pin and ground. This introduces negative feedback. If the transistor runs hot and tries to draw more current, the voltage across $R_S$ increases, which effectively reduces $V_{GS}$ and throttles the current back down.
- Recalculate Gate Bias: With $I_D = 2.72 mA$, the voltage at the source ($V_S$) is now $2.72 mA \times 470\Omega = 1.28V$. To maintain $V_{GS} = 2.15V$, your gate voltage ($V_G$) must be raised to $V_S + V_{GS} = 1.28V + 2.15V = 3.43V$.
- Bypass the Source Resistor for AC: $R_S$ stabilizes DC but kills AC gain. Place a 10µF electrolytic capacitor in parallel with $R_S$. This shorts the resistor for AC signals, restoring your voltage gain to the theoretical maximum while keeping the DC bias rock-solid.
- Verify with a Multimeter: Power the circuit with no AC input. Measure the drain pin. It should read between 5.5V and 6.5V. If it reads 11.8V, your transistor is off (gate voltage too low). If it reads 0.2V, it is fully saturated (gate voltage too high). Adjust your gate voltage divider resistors accordingly.
For further reading on stabilizing MOSFET bias networks against temperature variations, the MOSFET Amplifier guide on Electronics Tutorials provides excellent load-line visualizations.
By treating the NMOS not just as a theoretical component but as a physical device with manufacturing tolerances, you move from breadboard guesswork to reliable, repeatable amplifier design. Stick to the 2N7000 for low-frequency small-signal tasks, use source degeneration to lock in your bias, and let the transconductance do the heavy lifting.
