Understanding MOS Transistor Capacitance: The Hidden Speed Limit
When you select a MOSFET for a switching application, looking only at $R_{DS(on)}$ and maximum current is a fast track to blown gate drivers and massive EMI. The direct answer to why your high-frequency switch is overheating or ringing lies in MOS transistor capacitance. Every MOSFET contains three primary parasitic capacitances—$C_{iss}$ (input), $C_{oss}$ (output), and $C_{rss}$ (reverse transfer)—that dictate how fast the device can transition between states and how much peak current your gate driver must supply.
Look at the standard schematic symbol for an N-channel enhancement MOSFET. It has three main terminals: the Gate (G), Drain (D), and Source (S). Physically, the gate is a polysilicon layer separated from the semiconductor channel by a thin silicon dioxide insulator. This physical overlap between the gate and the drain/source diffusion regions creates tiny, unavoidable capacitors. In high-speed switching (like a 100kHz buck converter), these picofarad-range capacitors act like momentary dead shorts, demanding amps of instantaneous current to charge and discharge.
The Big Three: Ciss, Coss, and Crss Explained
Datasheets don't usually list the raw physical capacitances ($C_{gs}$, $C_{gd}$, $C_{ds}$). Instead, they provide the measurable terminal capacitances. Here is how they break down:
- $C_{iss}$ (Input Capacitance): $C_{gs} + C_{gd}$. This is the total capacitance your gate driver sees when the drain is AC-grounded. It determines the initial delay before the gate voltage reaches the threshold.
- $C_{oss}$ (Output Capacitance): $C_{ds} + C_{gd}$. This matters most during the off-state. When the MOSFET turns off, the energy stored in $C_{oss}$ ($E = \frac{1}{2} C_{oss} V_{ds}^2$) is dissipated as heat inside the silicon, limiting high-frequency efficiency.
- $C_{rss}$ (Reverse Transfer / Miller Capacitance): Simply $C_{gd}$. This is the most critical parameter for switching speed. As the drain voltage swings wildly during turn-on, it couples charge back through $C_{rss}$ to the gate, creating the infamous 'Miller plateau' that stalls the gate voltage rise.
| Region | $V_{gs}$ Condition | $V_{ds}$ Condition | Typical $I_d$ Behavior | Capacitance State |
|---|---|---|---|---|
| Cutoff | $< V_{th}$ (e.g., < 1.5V) | Any | 0A (Leakage only, ~µA) | $C_{oss}$ fully charged, max depletion width |
| Linear (Ohmic) | $> V_{th}$ (e.g., 4.5V) | $< V_{gs} - V_{th}$ | Proportional to $V_{ds}$ (acts as resistor) | $C_{gd}$ increases massively as $V_{ds}$ drops |
| Saturation (Active) | $> V_{th}$ (e.g., 4.5V) | $> V_{gs} - V_{th}$ | Constant current (set by $V_{gs}$) | Transitioning; Miller effect dominates |
Practical Biasing and a Real-World Switching Circuit
To properly bias and select a MOSFET, you must calculate the gate drive requirements based on the Total Gate Charge ($Q_g$), which is the integral of the capacitances over the switching voltage range. If you are driving the gate directly from a microcontroller GPIO (max 20-40mA), you are limited to low frequencies or must use a dedicated gate driver IC.
Below is a complete, bench-tested 12V PWM motor driver circuit using an ESP32 (3.3V logic) and a logic-level MOSFET.
Application Circuit: 12V DC Motor PWM Control
- Q1: IRLZ44N (Logic-level N-Channel, $V_{th}$ max 2.0V, fully enhanced at $V_{gs}$ = 4.5V)
- R1 (Gate Resistor): 100Ω. Limits peak GPIO current to ~33mA and damps the LC resonant tank formed by trace inductance and $C_{iss}$.
- R2 (Pull-down): 10kΩ from Gate to Source. Bleeds off $C_{gs}$ charge during MCU boot-up to prevent the motor from spinning erratically while the GPIO is high-impedance.
- D1 (Flyback): 1N5819 Schottky diode across the motor terminals (cathode to +12V). Clamps the inductive kickback that would otherwise avalanche the MOSFET's $C_{oss}$.
When the ESP32 drives the gate HIGH, current flows through R1 to charge $C_{iss}$. The gate voltage rises until it hits the Miller plateau (around 3V for this part). During this plateau, the drain voltage is falling, and the driver must source extra current to charge $C_{rss}$. Once the drain hits near-zero, the gate voltage rises to the full 3.3V, locking the FET in the low-resistance linear region.
Failure Modes and Multimeter Testing
Ignoring MOS transistor capacitance leads to specific, catastrophic failure modes. The most common is $dV/dt$ induced turn-on. In a half-bridge, when the high-side FET turns on, the switch node voltage spikes from 0V to 400V in nanoseconds. This massive $dV/dt$ pushes current through the low-side FET's $C_{rss}$ directly into its gate resistor. If the voltage drop across the gate resistor exceeds the $V_{th}$ of the low-side FET, it turns on momentarily. Both FETs conduct simultaneously (shoot-through), and they explode.
You can verify the health of a MOSFET's internal junctions and capacitances using a standard digital multimeter (DMM) in diode-test mode. Here is the definitive bench test:
- Discharge the Gate: Touch your finger across the Gate and Source pins, or use a 10kΩ resistor to short them. This drains any trapped charge in $C_{gs}$.
- Verify Off-State: Place the red probe on the Drain and the black probe on the Source. The DMM should read 'OL' (Open Loop), confirming the channel is off.
- Charge the Gate Capacitance: Move the red probe to the Gate while keeping the black probe on the Source. The DMM's internal battery (usually ~3V) will charge $C_{gs}$, turning the MOSFET on.
- Verify On-State: Move the red probe back to the Drain (black stays on Source). The DMM should now read a low voltage drop (typically 0.2V to 0.5V) or near 0Ω, proving the channel has enhanced and the FET is functional.
- Discharge and Re-verify: Short Gate to Source again. Re-test Drain to Source. It must return to 'OL'. If it stays shorted, the silicon is melted or the gate oxide is punctured.
Safe Default Part Numbers for Bench and PCB Designs
When you don't want to spend hours optimizing for $C_{rss}$, rely on these proven defaults. Always check the exact capacitance ratings for your specific switching frequency.
| Part Number | $V_{ds}$ / $I_d$ | $R_{DS(on)}$ @ 10V | $C_{iss}$ / $C_{rss}$ | Best Application |
|---|---|---|---|---|
| IRFZ44N | 55V / 49A | 17.5 mΩ | 1700 pF / 120 pF | Low-freq (<5kHz) high-current loads, automotive relays. Too much $C_{rss}$ for >50kHz. |
| IRLZ44N | 55V / 47A | 22 mΩ @ 5V | 1800 pF / 130 pF | Direct 3.3V/5V MCU logic-level driving at low frequencies. |
| CSD17571Q5A (TI) | 30V / 100A | 3.4 mΩ @ 4.5V | 850 pF / 12 pF | High-freq (>500kHz) buck converters, synchronous rectification. Ultra-low Miller charge. |
| IRFP460 | 500V / 20A | 270 mΩ | 4100 pF / 160 pF | Offline SMPS, high-voltage induction heating. Requires a robust ±15V gate driver. |
For a deeper mathematical breakdown of how these parasitics interact with gate driver impedance, refer to the comprehensive guides on Miller capacitance in MOSFETs by All About Circuits and the foundational MOSFET switching tutorials at Electronics Tutorials.
FAQ: MOS Transistor Capacitance Questions
Why does MOS transistor capacitance increase at lower drain voltages?
The capacitance between the drain and the gate/source is largely a junction capacitance formed by the reverse-biased PN body diode. The formula for a parallel plate capacitor is $C = \epsilon A / d$, where $d$ is the width of the depletion region. When $V_{ds}$ is high, the depletion region widens (increasing $d$), which lowers the capacitance. As the MOSFET turns on and $V_{ds}$ drops toward zero, the depletion region collapses, causing $C_{oss}$ and $C_{rss}$ to spike dramatically—often by a factor of 10x compared to their rated high-voltage values.
How does Miller capacitance cause shoot-through in half-bridge circuits?
In a half-bridge, the low-side MOSFET is held off by pulling its gate to ground. However, when the high-side MOSFET turns on, the switch node (connected to the low-side drain) spikes from 0V to the bus voltage (e.g., 400V) in nanoseconds. This massive $dV/dt$ forces a displacement current ($I = C_{rss} \times dV/dt$) through the low-side Miller capacitance. This current flows through the gate driver's pull-down resistor and internal impedance. If the resulting voltage spike ($V = I \times R$) exceeds the low-side FET's $V_{th}$, it turns on while the high-side is also on, creating a dead short across the power supply.
Can I use a larger gate resistor to fix MOSFET ringing caused by capacitance?
Increasing the gate resistor ($R_g$) will increase the damping factor of the parasitic LC tank formed by your PCB trace inductance and the MOSFET's $C_{iss}$, which can reduce high-frequency ringing on the gate node. However, this is a trade-off: a larger $R_g$ slows down the $dV/dt$ and $di/dt$ of the switching transition, drastically increasing switching losses and potentially causing the MOSFET to overheat. A better solution is to place a small ferrite bead (e.g., 600Ω at 100MHz) directly on the gate pin, or use an RC snubber across the drain-source to damp the drain ringing without sacrificing switching speed.
