Whether you are troubleshooting a US military schematic, reading a European industrial PLC ladder diagram, or reverse-engineering a faded PCB, recognizing the logic OR symbol and its hardware equivalents is fundamental to digital circuit diagnostics. Below is the complete reference data you need to identify, interpret, and test OR logic on the bench.
The Logic OR Symbol and Truth Table Reference
The table below maps the visual symbols used in schematics to their underlying Boolean math and physical silicon equivalents. Use this as your primary lookup when reading a new schematic.
| Standard | Symbol Shape | Boolean Expression | Truth Table (A, B → Y) | Common IC Part Numbers |
|---|---|---|---|---|
| ANSI/IEEE 91-1984 | Curved "D" shape (Military) | Y = A + B | 0,0→0 | 0,1→1 | 1,0→1 | 1,1→1 | 74HC32, CD4071, SN74LS32 |
| IEC 60617 | Rectangle with "≥1" qualifier | Y = A ∨ B | 0,0→0 | 0,1→1 | 1,0→1 | 1,1→1 | Same physical ICs, different schematic notation |
| ANSI (3-Input) | Curved "D" with 3 input lines | Y = A + B + C | Output is 1 if any input is 1 | 74HC4075, CD4075 |
| IEC (3-Input) | Rectangle with "≥1" and 3 inputs | Y = A ∨ B ∨ C | Output is 1 if any input is 1 | Same physical ICs |
Standard Variants: ANSI/IEEE vs. IEC 60617
The visual representation of the logic OR symbol depends entirely on the regional and industry standard adopted by the schematic's author. Understanding both prevents misinterpretation when working on international or legacy equipment.
ANSI/IEEE (The "Curved D")
Prevalent in the US, military documentation, and hobbyist platforms like Arduino and Raspberry Pi schematics. The ANSI/IEEE 91-1984 standard uses a distinctive shape: a flat back for the inputs and a curved, pointed front for the output. It is colloquially called the "military symbol." If you see this shape, you are looking at standard positive logic.
IEC 60617 (The "Rectangle")
Standard in Europe, international industrial automation, and modern PLC programming (often overlapping with IEC 61131-3 standards). The IEC rejects shape-based symbols in favor of rectangular blocks with internal alphanumeric qualifiers. The logic OR symbol in IEC is a simple rectangle containing ≥1. This literally reads: "The output is HIGH (1) if the sum of HIGH inputs is greater than or equal to 1."
- Confusing OR with XOR: The Exclusive-OR (XOR) gate looks nearly identical to the standard OR gate in ANSI format, but it features a double-curved input line (a second arc spaced slightly away from the flat back). In IEC, the XOR uses =1 instead of ≥1. An XOR outputs HIGH only when inputs differ; an OR outputs HIGH when any input is HIGH.
- Missing the Inversion Bubble: If there is a small circle (bubble) on the output pin of either the ANSI curved shape or the IEC rectangle, it is a NOR gate, not an OR gate. The bubble denotes logical inversion.
- Active-Low Inputs: Bubbles on the input lines mean the gate triggers on a LOW signal. An OR gate with active-low inputs behaves identically to a NAND gate in positive logic (De Morgan's Laws).
Interpreting Faded Silkscreen and Missing Markings
On older PCBs or heavily reworked boards, the logic OR symbol silkscreen may be scraped off or faded. Do not guess the logic function based on surrounding components. Instead, use this bench-testing decision path with a multimeter or logic probe:
- Identify the IC part number. If it reads
74HC32orCD4071, it contains four independent 2-input OR gates. - If the IC is unmarked (e.g., a custom ASIC or FPGA breakout), power the board and inject a logic LOW (0V) into Input B.
- Toggle Input A between LOW and HIGH while measuring Output Y. If Y perfectly follows A, it is likely an OR or XOR gate.
- To rule out XOR, hold Input A HIGH and toggle Input B. If Y stays HIGH when B goes HIGH, it is an OR gate. (An XOR gate would drop to LOW).
Hardware Implementation: 74HC32 and CD4071 Pinouts
When moving from schematic symbols to physical silicon, the Texas Instruments SN74HC32 and the legacy CD4071 are the most common quad 2-input OR gate ICs. Both use a standard 14-pin DIP (Dual In-line Package) footprint, but their electrical characteristics differ significantly.
| Pin Number | Function | 74HC32 (TTL/CMOS 5V) | CD4071 (CMOS 3-15V) |
|---|---|---|---|
| 1, 2 | Gate A Inputs | V_IH min = 3.15V (at 5V Vcc) | V_IH min = 3.5V (at 5V Vcc) |
| 3 | Gate A Output | t_pd ≈ 14ns | t_pd ≈ 60ns |
| 4, 5 | Gate B Inputs | Max I_out = ±25mA | Max I_out = ±6.8mA |
| 6 | Gate B Output | Fast edge rates | Slower, symmetric drive |
| 7 | GND | 0V Reference | 0V Reference |
| 8, 9 | Gate C Inputs | Standard CMOS thresholds | Standard CMOS thresholds |
| 10 | Gate C Output | High impedance when off | High impedance when off |
| 11, 12 | Gate D Inputs | Standard CMOS thresholds | Standard CMOS thresholds |
| 13 | Gate D Output | Standard CMOS thresholds | Standard CMOS thresholds |
| 14 | VCC | 2.0V to 6.0V | 3.0V to 15.0V |
Bench Tip for Unused Gates: A classic mistake when prototyping with the 74HC32 or CD4071 is leaving unused inputs floating. CMOS inputs have extremely high impedance; a floating pin will act as an antenna, picking up ambient EMI and causing the internal MOSFETs to oscillate rapidly between HIGH and LOW. This leads to excessive current draw, chip heating, and erratic behavior on adjacent gates. Always tie unused OR gate inputs to GND. Because 0 OR A = A, tying one input to ground allows the other input to pass through safely without forcing the output permanently HIGH.
For deeper theoretical background on how these physical gates map to Boolean algebra, refer to the All About Circuits Digital Logic Gates tutorial.
Frequently Asked Questions
What is the visual difference between a logic OR symbol and an XOR symbol?
In the ANSI/IEEE standard, the logic OR symbol is a single curved "D" shape. The XOR (Exclusive-OR) symbol is identical but features a second, parallel curved line drawn just outside the flat input edge. In the IEC 60617 standard, the OR gate is a rectangle marked with ≥1, while the XOR gate is a rectangle marked with =1. Functionally, an OR gate outputs HIGH if any input is HIGH, whereas an XOR gate outputs HIGH only if the inputs are different from each other.
How do I interpret a logic OR symbol with a circle on the output?
A small circle (often called a bubble or inversion circle) on the output line of a logic OR symbol indicates logical negation. This transforms the gate into a NOR gate. The Boolean expression changes from Y = A + B to Y = NOT(A + B). The output will only be HIGH when all inputs are LOW. If the circle is on an input line instead, it means that specific input is active-low.
Why do European schematics use a rectangle with "≥1" for the OR gate?
European and international industrial schematics follow the IEC 60617 standard, which abandoned the distinctive "military" shapes (like the curved D for OR or the triangle for AND) in favor of uniform rectangular blocks. The qualifier ≥1 inside the rectangle is a mathematical instruction: the output is true (1) if the number of true inputs is greater than or equal to 1. This standardized block approach makes it easier to draw complex, multi-input gates and custom programmable logic arrays without inventing new geometric shapes.
Can I wire unused OR gate inputs to VCC instead of GND?
While tying an unused OR gate input to VCC (logic HIGH) will prevent the floating-input oscillation problem, it is generally bad practice. Because of the OR truth table, if any input is HIGH, the output is forced HIGH regardless of the other input. This turns the gate into a permanent logic HIGH generator, wasting power and potentially back-feeding current into the output node if not properly isolated. Tying the unused input to GND (logic LOW) is the correct approach, as it allows the remaining input to control the gate normally (0 OR A = A).
