When hardware engineers and bench hobbyists search for a logic gate table, they are usually looking for one of two things: a Boolean truth table (AND, OR, NAND outputs) or the electrical specification matrix that dictates voltage thresholds, fan-out, and propagation delay. On the workbench, the truth table is trivial; the specification table is what prevents you from burning out an ESP32 GPIO pin, misinterpreting a noisy 5V bus, or chasing timing errors in a high-speed shift register.

This reference guide provides the master DC and AC characteristic tables for the most common logic families. We will cover how to read the threshold columns, how capacitive loading derates your timing margins, and the real-world PCB physics that datasheets leave out.

The Master Logic Family Specification Table

How to read this table: This data is derived from the JEDEC JESD8 standard for IC logic levels and cross-referenced with Texas Instruments Logic Family datasheets. The voltage thresholds ($V_{IL}$ and $V_{IH}$) assume a standard 25°C ambient temperature. $V_{IL}$ is the maximum voltage guaranteed to be read as a LOW; $V_{IH}$ is the minimum voltage guaranteed to be read as a HIGH. Propagation delay ($t_{pd}$) is measured at $V_{CC}$ nominal with a 15pF capacitive load.
Logic Family Standard Prefix $V_{CC}$ Range $V_{IL}$ (Max LOW) $V_{IH}$ (Min HIGH) Typical $t_{pd}$ Max DC Fan-Out
Standard TTL 74xx / SN7400 4.75V - 5.25V 0.8V 2.0V 10 ns 10 LS inputs
Standard CMOS 4000B / CD4000 3.0V - 15.0V 0.3 × $V_{CC}$ 0.7 × $V_{CC}$ 50 ns (at 5V) 1 (TTL) / 50 (CMOS)
HC (High-Speed CMOS) 74HCxx 2.0V - 6.0V 0.3 × $V_{CC}$ 0.7 × $V_{CC}$ 10 ns (at 5V) 25 (CMOS)
HCT (TTL-Compatible) 74HCTxx 4.5V - 5.5V 0.8V 2.0V 12 ns (at 5V) 25 (CMOS)
LVC (Low-Voltage CMOS) 74LVCxx 1.65V - 3.6V 0.3 × $V_{CC}$ 0.7 × $V_{CC}$ 3.5 ns (at 3.3V) 25 (LVC)
AHC (Advanced HC) 74AHCxx 2.0V - 5.5V 0.3 × $V_{CC}$ 0.7 × $V_{CC}$ 5.5 ns (at 5V) 25 (CMOS)

Bookmark Quick-Jump: Most Queried Interfacing Scenarios

  • 3.3V MCU to 5V Logic: Use 74HCT (e.g., SN74HCT00). A 3.3V ESP32 outputs ~2.9V HIGH. The HCT $V_{IH}$ is 2.0V, leaving a safe 0.9V noise margin. Do not use 74HC, which requires 3.5V to register a HIGH at a 5V supply.
  • 12V Automotive to 5V Logic: Use 4000B series (e.g., CD4011B) powered at 12V, followed by a voltage divider or level translator, as 12V directly into a 5V HCT input will destroy the gate.
  • 1.8V FPGA to 3.3V Bus: Use 74LVC (e.g., SN74LVC00A) powered at 3.3V. LVC inputs are 5.5V tolerant on many models, but always verify the specific datasheet for $V_{I}$ (absolute maximum input voltage) ratings.

Applying the Thresholds: Which Column Dictates Your Design?

When interfacing two different logic families or voltage domains, beginners often look only at the $V_{CC}$ column. This is a mistake. The columns that actually govern your design are the output thresholds of the driving chip ($V_{OH}$ and $V_{OL}$) mapped against the input thresholds of the receiving chip ($V_{IH}$ and $V_{IL}$).

To guarantee reliable switching, you must calculate the DC Noise Margin. The formulas are:

  • HIGH Noise Margin ($NM_H$): $V_{OH(min)} - V_{IH(min)}$
  • LOW Noise Margin ($NM_L$): $V_{IL(max)} - V_{OL(max)}$

Let us look at a concrete bench example. You are driving a 74HCT00 NAND gate (powered at 5V) with an ESP32-WROOM-32 GPIO pin (powered at 3.3V). Under a 4mA load, the ESP32 datasheet guarantees a $V_{OH}$ of roughly 2.9V. The 74HCT00 requires a $V_{IH}$ of 2.0V. Your HIGH noise margin is $2.9V - 2.0V = 0.9V$. This is an excellent margin for a breadboard environment.

Now, swap the receiver to a 74HC00 powered at 5V. The HC family requires a $V_{IH}$ of $0.7 \times V_{CC}$, which equals 3.5V. Your ESP32's 2.9V output falls 0.6V short of the threshold. The gate will either fail to switch or hover in the linear region, drawing massive quiescent current and overheating the IC. The $V_{IH}$ column is the ultimate arbiter of logic compatibility.

Bench Warning: Never rely on 'typical' values from a datasheet graph for threshold design. Always use the 'Min' and 'Max' guaranteed columns in the DC characteristics table. Temperature excursions and supply sag will push typical values out of spec.

Derating Propagation Delay and Fan-Out Under Load

The $t_{pd}$ (propagation delay) and Fan-Out rows in the logic gate table are not static numbers; they are baseline measurements taken under highly controlled, idealized conditions. In a real installation, parasitic capacitance and trace routing will derate these values significantly.

How Capacitive Load Derates Timing

The typical $t_{pd}$ row in our master table assumes a capacitive load ($C_L$) of 15pF to 50pF, representing one or two standard logic inputs and a short PCB trace. Every time you add an input to the bus, or route a longer trace, you add capacitance.

For standard HC and LVC families, the derating factor is roughly 0.3ns to 0.5ns per additional 10pF of load. If your 74HC00 is driving a bus with 6 inputs (approx. 3pF each) plus a 10cm FR4 trace (approx. 2pF per cm), your total $C_L$ might be 40pF above the baseline. You must add ~2.0ns to the baseline $t_{pd}$. In a 20MHz SPI clock line, a 2ns skew between the clock and data lines can cause setup/hold time violations and corrupted bytes.

The Myth of DC Fan-Out

The 'Max DC Fan-Out' column is largely a legacy metric from the bipolar TTL era, where gates drew significant DC input current. Modern CMOS inputs (HC, LVC, AHC) draw virtually zero DC current (typically <1µA). Therefore, the DC fan-out is practically infinite.

However, AC Fan-Out is the real limiting factor. Each CMOS input presents a small capacitance (typically 3pF to 5pF). If you hang 20 CMOS inputs on a single output pin, the driving gate must source and sink the transient current ($I = C \times dV/dt$) to charge and discharge 100pF of total capacitance. This slows down the rise and fall times, increases propagation delay, and causes the driving IC to run hot. Keep AC fan-out below 10 for high-speed buses.

What the Datasheet Table Cannot Tell You

While the logic gate table provides the foundational DC and AC limits, it completely ignores the physics of the printed circuit board. When debugging ghost-triggering or erratic outputs on the bench, you must look beyond the silicon specifications.

Simultaneous Switching Noise (SSN) and Ground Bounce

Datasheet tables assume an ideal, zero-impedance ground. In reality, every IC package lead and PCB via has parasitic inductance. When multiple outputs on a 74LVC245 buffer switch from HIGH to LOW simultaneously, the sudden rush of current through the ground pin's inductance creates a voltage spike ($V = L \times di/dt$).

This spike lifts the internal ground reference of the chip relative to the PCB ground plane—a phenomenon known as ground bounce. If the bounce exceeds a few hundred millivolts, an adjacent input pin reading a steady LOW might momentarily cross the $V_{IL}$ threshold, registering a false HIGH pulse. The logic gate table will not warn you about this; mitigating it requires placing 100nF decoupling capacitors within 2mm of the $V_{CC}$ pin and using wide, low-inductance ground planes.

Input Hysteresis and Slow Edges

Standard logic gates do not have Schmitt-trigger inputs unless explicitly noted (e.g., 74HC14). If your input signal has a slow rise time (like an RC-filtered PWM or a mechanical switch without debouncing), the signal will linger in the undefined region between $V_{IL}$ and $V_{IH}$. During this window, internal transistor pairs can oscillate wildly, causing high-frequency ringing, massive current draw, and multiple false clock edges. Always use Schmitt-trigger buffers (like the 74HC14 or 74LVC1G17) when conditioning slow-moving analog or mechanical signals into digital logic domains.

By treating the logic gate table not as a static cheat sheet, but as a dynamic baseline that must be derated for capacitance, noise margins, and PCB parasitics, you will eliminate the most common digital interfacing failures before you even power up the bench supply.