When you transition from writing Boolean algebra on paper to wiring physical 74-series logic ICs or routing traces in an EDA tool, you need a reliable translation layer. The symbols for truth tables serve as that bridge, mapping abstract logical operations (AND, OR, XOR) to the physical schematic shapes you will solder, probe, and debug. However, a major stumbling block for hobbyists and junior engineers is the existence of two competing visual standards: the distinct-shape ANSI/IEEE standard and the rectangular IEC standard.

This reference chart provides the exact mappings, explains how modifier symbols alter base logic states, and details the real-world electrical characteristics that a simple truth table completely hides.

How to Read This Logic Symbol Reference Chart

Before jumping to the data, you need to know which symbol standard applies to your specific installation or design workflow. The table below is divided into two primary visual columns:

  • ANSI/IEEE Std 91-1984 (Distinct Shapes): This is the default for most US-based hobbyists, legacy schematics, and educational textbooks. If you are using LTspice, Fritzing, or older US military/industrial prints, you will use these D-shaped, curved, and triangular symbols.
  • IEC 60617-12 (Rectangular Symbols): This is the standard for modern European industrial designs, IEC-compliant PLC programming, and newer EDA tools like Altium Designer or KiCad (when configured to IEC). Every gate is a rectangle with a specific qualifier symbol inside (like & for AND or 1 for OR).
How Inversion Bubbles Modify the Base Value: In both standards, a small circle (a 'bubble') on an input or output pin acts as a logical NOT modifier. It inverts the base logic state. If an AND gate (which requires all HIGH inputs to output HIGH) has a bubble on its output, it becomes a NAND gate. In IEC symbols, this is represented by a small triangle or circle on the pin line, and the internal symbol changes to reflect the inverted output condition.

Complete Logic Gate Symbols and Truth Table Reference

Source Standards: ANSI/IEEE Std 91-1984 (Graphic Symbols for Logic Functions) and IEC 60617-12 (Graphical Symbols for Diagrams - Binary Logic Elements).

Quick-Jump Bookmarks: AND | OR | NOT | NAND | NOR | XOR | XNOR

Gate Type Boolean Expression ANSI/IEEE Shape (US) IEC 60617 Shape (EU) Truth Table Output (Y)
AND Y = A · B Flat back, curved D-shaped front Rectangle with internal & HIGH only if ALL inputs are HIGH
OR Y = A + B Curved back, pointed front (shield shape) Rectangle with internal ≥1 HIGH if ANY input is HIGH
NOT (Inverter) Y = A' Triangle pointing right, bubble on output Rectangle with internal 1, triangle on output Opposite of input state
NAND Y = (A · B)' AND shape with bubble on output Rectangle with &, triangle on output LOW only if ALL inputs are HIGH
NOR Y = (A + B)' OR shape with bubble on output Rectangle with ≥1, triangle on output HIGH only if ALL inputs are LOW
XOR Y = A ⊕ B OR shape with extra curved line on back Rectangle with internal =1 HIGH if inputs are DIFFERENT
XNOR Y = (A ⊕ B)' XOR shape with bubble on output Rectangle with =1, triangle on output HIGH if inputs are the SAME

What Symbols and Truth Tables Cannot Tell You

A truth table and its corresponding logic symbol represent ideal, instantaneous Boolean math. When you move from a textbook to a workbench with a Texas Instruments SN74HC08N quad AND gate, the physical reality of silicon introduces variables the symbol completely hides.

1. Propagation Delay ($t_{pd}$)

Truth tables imply that when Input A goes HIGH, Output Y goes HIGH instantly. In reality, a standard 74HC series gate at 5V has a propagation delay of roughly 14 nanoseconds. If you are designing a high-speed clock divider or a precision pulse-width modulator, those 14ns delays compound through cascaded gates, leading to timing skew and potential metastability in downstream flip-flops.

2. Voltage Thresholds ($V_{IH}$ and $V_{IL}$)

The symbols show binary 1s and 0s, but silicon sees analog voltages. For a 5V 74HC CMOS chip, a logic HIGH ($V_{IH}$) isn't strictly 5V; it is guaranteed to be recognized as a '1' anywhere above 3.15V. Conversely, a logic LOW ($V_{IL}$) is anything below 1.35V. The 1.8V gap in between is the undefined transition region. If your input signal lingers in this zone due to a slow RC rise time, the gate will oscillate and draw massive amounts of shoot-through current, potentially overheating the IC.

3. Fan-Out and Drive Current

A truth table doesn't tell you how many subsequent gates you can connect to a single output. A standard 74LS TTL gate can sink about 8mA ($I_{OL}$) but only source 0.4mA ($I_{OH}$). If you wire one LS output to ten LS inputs, you will exceed the HIGH-state fan-out limit, causing the voltage to droop below the $V_{IH}$ threshold and resulting in phantom logic errors. Always check the datasheet for $I_{OH}$ and $I_{OL}$ rather than trusting the schematic symbol.

Frequently Asked Questions

What is the difference between ANSI and IEC symbols for truth tables?

The ANSI/IEEE standard uses distinct geometric shapes (D-shapes, shields, triangles) to represent the function of the gate visually. The IEC 60617 standard uses uniform rectangular boxes for all gates, relying on internal text qualifiers (like & for AND, ≥1 for OR, and =1 for XOR) to define the logic. ANSI is dominant in US academia and hobbyist spaces, while IEC is preferred in European industrial automation and complex VLSI design where drawing distinct shapes for thousands of gates becomes visually cluttered.

How do I read an active-low symbol with a bubble on the input?

A bubble on an input pin means the gate expects a LOW signal to trigger that specific input's condition. For example, a flip-flop with a bubble on the 'Clear' pin means the chip will reset when that pin is pulled to GND (active-low). In schematic design, we often use De Morgan's equivalents to match bubbles: if a NAND gate (bubble on output) drives an active-low input (bubble on input), the bubbles 'cancel' out logically, indicating a direct, non-inverted signal path for that specific condition.

Why does my XOR truth table symbol look different in KiCad versus LTspice?

EDA tools have different default libraries. LTspice strictly adheres to the ANSI/IEEE distinct shapes, so your XOR will look like a shield with a detached curved back line. KiCad defaults to ANSI shapes in its standard library but includes IEC rectangular symbols in its secondary libraries. Furthermore, some older schematic capture tools use a simplified 'rectangle with an X' for XOR, which is technically non-compliant with both modern IEEE and IEC standards but persists in legacy documentation.

Can I use a NAND gate to build any other logic symbol?

Yes. The NAND gate is known as a 'universal gate.' By wiring the inputs of a NAND gate together, you create a NOT gate (inverter). By cascading NAND gates, you can construct AND, OR, NOR, and XOR functions. This is why early silicon designers often built entire microprocessors using only NAND gates—it simplified the manufacturing mask layers. If you are stuck with a hex-inverter chip and a quad-NAND chip (like the 74HC00) on your bench, you can synthesize any missing logic function you need for a quick prototype fix.