Whether you are troubleshooting a legacy 7400-series TTL board or designing a new FPGA state machine, reading logic diagram symbols correctly is non-negotiable. Misinterpreting a single bubble or arc can lead you down hours of wrong diagnostic paths. Below is the complete reference mapping the two dominant global standards, followed by practical guidance on regional variants and faded schematic recovery.

The Master Logic Diagram Symbols Reference Table

This table maps the seven fundamental logic gates across the two primary drafting standards, alongside their Boolean equivalents and the most common physical ICs you will encounter on a bench.

Gate Function IEEE/ANSI Shape IEC 60617 Identifier Boolean Expression Common 74xx/40xx IC
AND D-Shape (Flat back, curved front) & A · B 74HC08 / CD4081
OR Curved back, pointed front ≥1 A + B 74HC32 / CD4071
NOT (Inverter) Triangle with output bubble 1, small circle on output A' 74HC04 / CD4049
NAND D-Shape with output bubble &, small circle on output (A · B)' 74HC00 / CD4011
NOR Curved back with output bubble ≥1, small circle on output (A + B)' 74HC02 / CD4001
XOR OR shape with extra input arc =1 A ⊕ B 74HC86 / CD4030
XNOR XOR shape with output bubble =1, small circle on output (A ⊕ B)' 74HC266 / CD4077

Regional Standards: IEEE Distinctive Shapes vs. IEC Rectangular Outlines

Logic diagram symbols are not universal; they are strictly governed by regional and industry standards. Knowing which standard applies to your schematic prevents catastrophic misreads, especially when working with imported industrial equipment or legacy military hardware.

IEEE Std 91 (ANSI Y32.2): The Distinctive Shape Standard

Dominant in the United States, Japan, and most academic textbooks, the IEEE standard relies on distinctive shapes. The physical outline of the gate (D-shape for AND, curved for OR) tells you its function. Inversion is always denoted by a small circle (a "bubble") on the input or output line. This standard is heavily used in digital electronics education and consumer electronics schematics.

IEC 60617-12: The Rectangular Outline Standard

Mandatory in Europe and heavily favored in international industrial automation (PLCs, motor drives), the IEC standard discards distinctive shapes entirely. Every gate is drawn as a rectangle. The function is identified by a text symbol inside the box (e.g., & for AND, ≥1 for OR). Inversion is shown by a small circle on the pin, or occasionally by a half-arrowhead indicating active-low logic.

Feature IEEE Std 91 (US/Global Hobbyist) IEC 60617 (EU/Industrial PLC)
Visual Style Distinctive geometric shapes Uniform rectangular boxes
Function ID Outline shape (D, curve, triangle) Internal text qualifier (&, ≥1, =1)
Inversion Marker Small circle (bubble) Small circle or right-pointing triangle
Primary Use Case PCB design, microcontrollers, academia Ladder logic, industrial HMIs, IEC 61131-3
⚠️ Standard Mixing Hazard: Never assume a schematic uses only one standard. It is common for a US-based systems integrator to drop an IEC-standard PLC block diagram into an IEEE-standard board-level schematic. Always check the title block for the governing drafting standard (e.g., "ANSI Y32.2" or "IEC 60617") before tracing signals.

Rows People Get Wrong and Faded Schematic Recovery

Even experienced engineers misread specific logic diagram symbols, particularly when dealing with negative logic or degraded documentation. Here is how to handle the most common pitfalls and safely interpret unreadable schematics.

The "Rows People Get Wrong" Notes

  • The XOR vs. OR Trap: In the IEEE standard, the XOR gate is drawn exactly like an OR gate, but with a second, disconnected curved line near the inputs. On low-resolution PDF scans, faxed documents, or heavily copied blueprints, this extra arc vanishes. Rule of thumb: If the circuit is a parity checker, an adder, or a phase detector, it is almost certainly an XOR (74HC86), even if the extra arc is missing.
  • De Morgan’s Equivalents (Negative Logic): You will frequently see a NAND gate drawn with bubbles on its inputs rather than its output. Logically, an AND gate with inverted inputs is identical to a NOR gate. Designers do this intentionally to show signal intent. If the inputs are active-low chip selects (e.g., /CS1 and /CS2), drawing it as an OR gate with input bubbles tells the reader: "This output goes high when either of these active-low signals is triggered." Do not "correct" the schematic in your head to a standard NOR gate; you will lose the active-low context.
  • The IEC "1" vs "≥1" Confusion: In IEC diagrams, a buffer or inverter is marked with a 1 inside the rectangle, while an OR gate is marked with ≥1. If the bottom of the "≥" symbol is faded, a 3-input OR gate looks exactly like a buffer, leading to massive troubleshooting errors when the third input is ignored.

Safe Interpretation When Markings are Faded or Missing

When working on legacy equipment (e.g., 1980s CNC controls or vintage audio synths), schematics are often physically degraded, and logic symbols may be entirely obscured by coffee stains or toner drift. Never guess the gate function based on surrounding context alone.

  1. Identify the Silicon: Ignore the faded symbol and look at the physical IC on the board. If you can read SN74LS00N, you are looking at a Quad 2-Input NAND gate. Pull up the manufacturer datasheet to confirm the pinout. The silicon never lies, even if the paper does.
  2. Build a Physical Truth Table: If the IC part number is scraped off, power the board (if safe) and use a logic probe. A basic TTL/CMOS logic probe (like the $15 Elenco LP-560) will pulse high, low, or show a pulse train. Stimulate the inputs with a logic pulser or jumper wire, and record the output state for all four permutations (00, 01, 10, 11). Match your physical truth table to the master table above.
  3. Check for Open-Collector Outputs: If your physical truth table shows a "floating" or weak high state, the gate might be an open-collector/open-drain variant (e.g., 7403 instead of 7400). Look for a 4.7kΩ to 10kΩ pull-up resistor on the output trace. IEEE standard documentation denotes open-collector outputs with a specific diamond symbol inside the gate, but this is the first detail to fade on old blueprints.

By relying on the physical IC part number and empirical truth-table testing rather than squinting at degraded ink, you eliminate the guesswork and protect the downstream circuitry from incorrect diagnostic assumptions.