The inverting op amp circuit produces an output voltage that is proportional to the input voltage but shifted 180 degrees out of phase. The closed-loop voltage gain is defined strictly by two external resistors: Av = -Rf / Rin. If you need a predictable, stable gain with a virtual ground summing node, this is your baseline topology. Unlike open-loop comparators, this configuration uses negative feedback to force the differential input voltage to near zero, creating a highly linear amplifier limited only by the op-amp's gain-bandwidth product and slew rate.

Topology Nodes and Element Behavior Matrix

To design reliably, you must understand the four critical nodes in this topology:

  • Vin (Input): The signal source, connected through the input resistor.
  • V- (Inverting Input / Summing Junction): The 'virtual ground' node where input and feedback currents sum.
  • V+ (Non-Inverting Input): Typically tied to ground (0V) or a reference voltage to set the DC bias point.
  • Vout (Output): The amplified, inverted signal driving the load.

Because the op-amp's open-loop gain is massive (often >100,000), the negative feedback through Rf forces the V- node to match the V+ node. If V+ is grounded, V- becomes a virtual ground. It sits at 0V, but sinks current unlike a physical ground connection.

Bench Tip: Never assume a virtual ground can sink infinite current. The current flowing into the summing junction must exit through the feedback resistor. If your op-amp output hits the supply rail (clips), the virtual ground collapses, and V- will no longer sit at 0V.

Behavior Table: What Changes When You Alter an Element?

Element Changed Modification Effect on Gain (Av) Effect on Circuit Behavior
Feedback Resistor (Rf) Increase value Increases (more negative) Higher gain, but reduces closed-loop bandwidth and increases thermal noise at the output.
Input Resistor (Rin) Decrease value Increases (more negative) Lowers the circuit's input impedance, potentially loading down high-impedance signal sources.
Non-Inverting Pin (V+) Tied to Vref instead of GND Unchanged (AC gain) Shifts the entire output DC operating point by Vref * (1 + Rf/Rin).
Op-Amp IC Swap to lower Slew Rate Unchanged (DC/Low Freq) High-frequency or high-amplitude signals will distort into triangular waves (slew-induced distortion).

Inverting vs. Non-Inverting: Why Choose This Topology?

Beginners often default to the non-inverting topology because it doesn't flip the signal phase and offers massive input impedance. However, the inverting op amp circuit solves specific engineering problems that the non-inverting variant cannot.

Criterion Inverting Topology Non-Inverting Topology
Input Impedance Low (Exactly equal to Rin) Extremely High (Op-amp common-mode impedance)
Phase Shift 180 degrees (Inverted) 0 degrees (In-phase)
Signal Summing Excellent (Virtual ground prevents crosstalk) Poor (Signals interact via resistor network)
Common-Mode Voltage Zero (V- and V+ are fixed at ground) Varies with input signal (Requires high CMRR)

Choose the inverting topology when: You are building an audio mixer (summing multiple inputs into the virtual ground), driving a low-impedance source that doesn't care about loading, or when you need to eliminate common-mode voltage errors in precision DC measurements.

Design Walkthrough: Building a -10x Gain Audio Preamp

Let's design a practical inverting amplifier for a line-level audio signal. We need a gain of -10 (20 dB) and low noise.

Component Selection

  • Op-Amp: TL072 (Dual JFET-input op-amp, excellent for audio due to low voltage noise and high slew rate).
  • Target Gain: -10.
  • Rin: 10 kΩ. This sets our input impedance to 10k, a standard matching impedance for pro-audio line-level gear.
  • Rf: 100 kΩ. (Gain = -100k / 10k = -10).
  • Rcomp (Bias Compensation): 9.1 kΩ. Placed between the V+ pin and ground.
Why Rcomp? Real op-amps draw a tiny 'input bias current' into their input pins. If the DC resistance seen by the V- pin (Rin || Rf = 10k || 100k ≈ 9.09kΩ) doesn't match the resistance seen by the V+ pin, this bias current creates an unwanted DC offset voltage at the output. While JFET inputs like the TL072 have bias currents in the picoamp range (making Rcomp optional), it is mandatory practice for bipolar op-amps like the LM741 or NE5532. See Analog Devices MT-038 for the math.

Power and Bypassing

Power the TL072 with a dual supply: +12V on Pin 8, -12V on Pin 4. Place a 100nF (0.1μF) MLCC ceramic capacitor from Pin 8 to ground, and another from Pin 4 to ground. Keep these capacitors within 5mm of the IC pins to shunt high-frequency supply noise and prevent parasitic oscillation.

Breadboard Testing and Extreme Failure Modes

Before soldering, validate the circuit on a breadboard. Follow this exact sequence to avoid blowing the IC or chasing ghost oscillations.

Step-by-Step Breadboard Test

  1. De-energize: Ensure the power supply is OFF and discharged.
  2. Place IC: Insert the TL072 across the center trench. Pin 1 is top-left.
  3. Route Power & Bypass: Connect +12V to Pin 8, -12V to Pin 4. Install the 100nF bypass caps immediately adjacent to the power pins.
  4. Establish Ground Reference: Tie Pin 3 (V+) to ground through the 9.1kΩ Rcomp resistor.
  5. Wire Feedback: Connect the 100kΩ Rf resistor from Pin 2 (V-) to Pin 1 (Output of channel A).
  6. Wire Input: Connect the 10kΩ Rin resistor from your signal source to Pin 2.
  7. Verify & Power On: Check for shorts with a multimeter in continuity mode. Turn on the dual supply.
  8. Measure DC Offset: With the input grounded, measure Pin 1 with your DMM. It should read < 5mV. If it reads near +12V or -12V, your feedback loop is broken.

What Breaks at the Extremes? (Failure Mode Contrast)

Understanding how the circuit fails when a component goes open or short is critical for troubleshooting.

  • Rf goes OPEN: The negative feedback loop is broken. The op-amp runs in open-loop mode. The microscopic input offset voltage is multiplied by 100,000+, and the output instantly slams into the positive or negative supply rail (clipping).
  • Rf goes SHORT: The output is directly tied to the V- pin. The circuit becomes a unity-gain voltage follower tied to ground. The output will sit at 0V regardless of the input signal.
  • Rin goes OPEN: No input current can reach the summing junction. The output will sit at 0V (plus any minor DC offset), completely ignoring the input signal.
  • V+ (Pin 3) left FLOATING: A classic beginner mistake. The high-impedance pin acts as an antenna, rectifying stray RF noise and EMI. The output will exhibit massive, unpredictable low-frequency drift or lock up against a supply rail.

Pushing the Extremes: Bandwidth and Slew Rate Limits

The formula Av = -Rf / Rin assumes an ideal op-amp. In reality, Texas Instruments application notes on op-amp parameters remind us that gain and bandwidth are inversely linked by the Gain-Bandwidth Product (GBP).

The TL072 has a typical GBP of 3 MHz. If you set your closed-loop gain to 10 (20 dB), your maximum usable bandwidth drops to:

Bandwidth = GBP / Gain = 3,000,000 Hz / 10 = 300 kHz.

This is perfectly adequate for audio (20 Hz - 20 kHz). However, if you attempt to use this exact same -10x circuit to amplify a 1 MHz RF signal, the op-amp will have virtually zero gain left. For RF applications, you must select a specialized high-speed op-amp like the OPA656 (GBP > 200 MHz).

Finally, watch the slew rate. The TL072 can change its output voltage at a maximum rate of 13 V/μs. If you feed it a 100 kHz square wave at 20V peak-to-peak, the required slew rate is roughly 12.5 V/μs. You are right on the edge of the IC's physical limits, and the square wave corners will begin to round off into trapezoids. Always calculate your maximum dV/dt requirements before finalizing your BOM.