The inverting amplifier circuit produces an output voltage that is 180 degrees out of phase with the input, scaled precisely by the ratio of the feedback resistor to the input resistor. The governing equation is Vout = -Vin × (Rf / Rin). Unlike non-inverting topologies, this configuration anchors the non-inverting input to ground, creating a 'virtual ground' at the inverting input. This makes it the definitive choice for summing mixers, active filters, and applications requiring signal attenuation (gain < 1) alongside amplification.

Topology and Node Definitions

To design or troubleshoot this circuit, you must understand the four critical nodes in the standard topology. We assume an ideal op-amp with infinite open-loop gain and infinite input impedance.

  • Node 1 (Vin): The signal source. The input impedance of the entire circuit is simply the value of Rin, because Node 2 is held at virtual ground.
  • Node 2 (Inverting Input / Pin 2): The summing junction. Due to negative feedback, the op-amp drives its output to keep the voltage difference between Node 2 and Node 3 at zero. Since Node 3 is at 0V, Node 2 sits at a 'virtual ground' (0V, but not physically connected to ground).
  • Node 3 (Non-Inverting Input / Pin 3): Tied directly to the system ground (0V reference).
  • Node 4 (Vout / Pin 6): The output node, sourcing or sinking current to maintain the virtual ground at Node 2.

Because Node 2 is at virtual ground, the current flowing through Rin is exactly Vin / Rin. Since the op-amp's input impedance is infinite, no current flows into Pin 2. Therefore, that exact same current must flow through Rf to Node 4, generating the inverted output voltage drop. For a deeper mathematical derivation of these node equations, refer to the Texas Instruments application note on op-amp circuit design.

Component Behavior and Extreme Failure Modes

When an inverting amplifier misbehaves on the bench, it is almost always due to a broken feedback path or an input short. The table below maps exactly what happens to Vout when a single component fails open or shorted. Keep this on your bench for rapid troubleshooting.

Component Fault Condition Effect on Vout Physical Consequence & Diagnosis
Rf (Feedback) Open Saturates to positive or negative rail Loss of negative feedback. Op-amp operates in open-loop mode, amplifying microvolt offset errors to the maximum supply rail. Measure Pin 6 to GND; if it reads exactly +Vcc or -Vee, check Rf continuity.
Rf (Feedback) Shorted 0V (or tiny mV offset) Gain becomes 0. Vout is forced to equal the virtual ground at Pin 2. Circuit acts as a dead short to the signal source's current.
Rin (Input) Open 0V (or tiny mV offset) No input current can flow. The feedback loop holds Pin 2 and Pin 6 at ground potential. Output appears dead regardless of Vin.
Rin (Input) Shorted Saturates to rail Gain approaches infinity. Vin is applied directly to Pin 2, breaking the virtual ground assumption and slamming the output to the rail.
Op-Amp Power Vcc/Vee Missing 0V or floating Internal transistors are off. Pin 6 may float or read 0V. Always verify pins 8 and 4 with a multimeter before chasing signal path issues.

Inverting vs. Non-Inverting: Why Choose This Topology?

Beginners often default to the non-inverting topology because it doesn't flip the signal phase and offers massive input impedance. However, the inverting amplifier circuit solves specific engineering problems that the non-inverting variant cannot. Here is the decision matrix for choosing between them.

Design Criteria Inverting Amplifier Non-Inverting Amplifier
Minimum Gain Can attenuate (Gain < 1, e.g., 0.5x) Minimum gain is +1 (Unity buffer)
Input Impedance Low (Equal to Rin) Extremely High (Op-amp common-mode Z)
Summing Signals Excellent (Virtual ground isolates inputs) Poor (Inputs interact via resistor network)
Phase Shift 180° (Inverted) 0° (In-phase)
Common-Mode Voltage 0V (Fixed at ground) Varies with Vin (Can trigger CMRR limits)
Pro Tip: If your signal source has a high output impedance (like a passive guitar pickup or a high-value voltage divider), the inverting topology will load it down and cause signal loss because Zin = Rin. In those cases, buffer the signal with a unity-gain non-inverting op-amp first, then feed it into your inverting gain stage.

Design Walkthrough: -10x Gain Audio Stage with TL072

Let's build a practical inverting amplifier circuit with a gain of -10, suitable for an audio line-level preamp or sensor signal scaling. We will use the TL072CP (DIP-8 package), a JFET-input dual op-amp prized for its low noise (18 nV/√Hz) and high slew rate (13 V/μs).

Component Selection

  • U1: TL072CP (Pins: 1=Out A, 2=Inv A, 3=Non-Inv A, 4=Vee, 5=Non-Inv B, 6=Inv B, 7=Out B, 8=Vcc)
  • Rin: 10 kΩ (1% metal film). Sets input impedance to 10kΩ.
  • Rf: 100 kΩ (1% metal film). Gain = -100k / 10k = -10.
  • Rcomp: 9.1 kΩ. Placed between Pin 3 and GND to match the DC resistance seen by Pin 2 (10k || 100k ≈ 9.09k). Note: Because the TL072 uses JFET inputs with picoamp-level bias currents, this resistor is technically optional for DC offset, but it is mandatory if you swap to a bipolar op-amp like the NE5532 or LM741.
  • Decoupling: Two 100 nF X7R MLCC capacitors (one from Pin 8 to GND, one from Pin 4 to GND), placed within 5mm of the IC body.

Bandwidth and Slew Rate Check

The TL072 has a typical Gain-Bandwidth Product (GBP) of 3 MHz. At a closed-loop gain of 10, our small-signal bandwidth is 3 MHz / 10 = 300 kHz, which easily covers the 20 Hz - 20 kHz audio spectrum. Furthermore, with a ±12V supply and a 13 V/μs slew rate, the maximum full-power frequency before slew-induced distortion is roughly 170 kHz. We are well within safe operating margins.

Breadboard Verification Steps

Do not just plug in the chip and apply an audio signal. Follow this systematic power-up and verification sequence to avoid blowing the output stage or chasing ghost oscillations. For more on preventing high-frequency oscillation on the bench, consult the Analog Devices guide on avoiding common op-amp mistakes.

  1. Set the Power Rails: Configure your bench supply to output +12V and -12V relative to a common ground. Do not connect the op-amp yet. Verify the voltages with your multimeter.
  2. Seat the IC and Decouple: Place the TL072 across the breadboard center trench. Install the 100 nF ceramic capacitors from Pin 8 to the ground rail, and Pin 4 to the ground rail. Connect the power rails to Pins 8 and 4.
  3. Wire the Feedback and Ground: Install Rf (100k) between Pin 2 and Pin 6. Install Rcomp (9.1k) from Pin 3 to ground. Leave Rin disconnected for the first test.
  4. Quiescent Current & Offset Test: Power on the supply. Measure the voltage at Pin 6 (Output). With Pin 2 floating (or tied to Pin 3 via a temporary jumper), the output should read between -5mV and +5mV. If it reads ±11V, your feedback loop is open or the chip is dead.
  5. Install Input Resistor: Power down. Install Rin (10k) from your signal input point to Pin 2. Power back up.
  6. Inject Signal and Verify: Apply a 1 kHz sine wave at 100 mV peak-to-peak from your function generator to the input side of Rin. Probe the output with an oscilloscope. You should see a 1 V peak-to-peak sine wave, perfectly inverted (180° phase shift) relative to the trigger channel.
Warning - Oscillation Trap: If your oscilloscope shows a fuzzy, thick trace or a high-frequency sine wave superimposed on your 1 kHz signal, your circuit is oscillating. This is almost always caused by long breadboard jumper wires acting as antennas, or missing decoupling capacitors. Keep Rf and Rin as physically close to Pin 2 as possible to minimize parasitic capacitance at the summing junction.

By understanding the virtual ground node, respecting the failure modes of the feedback network, and carefully managing parasitic capacitance on the breadboard, the inverting amplifier becomes a highly predictable and robust building block for any analog signal chain.