Designing a High-Current MOSFET Power Supply: Synchronous Buck vs. Linear Pass

When engineers and makers refer to a MOSFET power supply, they are typically describing one of two architectures: a linear regulator utilizing a MOSFET as the pass element, or a switched-mode power supply (SMPS) relying on MOSFETs for high-frequency switching. For high-current auxiliary rails in 24V battery, solar, and UPS systems—such as stepping down a 24V nominal bus to a 5V, 10A (50W) logic rail—the topology you choose dictates your thermal management strategy, PCB real estate, and electromagnetic interference (EMI) profile.

The direct answer for a 24V-to-5V, 10A load is to use a synchronous buck converter. A linear MOSFET pass regulator at this voltage differential will dissipate 190W of heat, requiring massive, expensive heatsinking. A synchronous buck converter achieves over 90% efficiency, dissipating less than 5W, which can be managed entirely through PCB copper pours. Below, we break down the exact physics, component selection, and layout rules required to build this supply.

Topology Showdown: Linear Pass vs. Synchronous MOSFET Switching

Before selecting gate drivers and inductors, we must quantify the trade-offs between the three primary MOSFET-based step-down topologies. The most common mistake in power supply design is selecting a topology based on component cost alone, ignoring the system-level cost of thermal management and enclosure size.

The Linear Dropout and Headroom Math

Why is the linear MOSFET pass topology disqualified for this load? Let us look at the headroom math. To regulate 5V from a 24V source, the MOSFET must drop 19V. At 10A, the power dissipated as heat is P = V_drop × I_load = 19V × 10A = 190W. Even if you mount the MOSFET to an extruded aluminum heatsink with a thermal resistance of 0.5°C/W, the junction temperature rise will be 95°C above ambient. In a 40°C enclosure, your silicon junction hits 135°C, dangerously close to the 150°C or 175°C maximum rating, leaving zero margin for transient load spikes. Linear pass designs are strictly reserved for low-dropout scenarios (e.g., 5V to 3.3V at 1A) or ultra-low-noise RF applications where switching noise is unacceptable.

Design Example: 24V-to-5V @ 10A Synchronous Buck Converter

For our 50W synchronous buck design, we will use a wide-input voltage controller driving discrete N-channel MOSFETs. Integrated converters (which bundle the controller and MOSFETs into a single QFN package) often struggle with thermal throttling at 10A when the input-to-output differential is this high. Discrete MOSFETs allow us to spread the heat across the PCB.

Component Selection and the Duty Cycle Trap

The core of this design relies on understanding the duty cycle (D). For a 24V input and 5V output, D = Vout / Vin = 5 / 24 = 0.208. The high-side MOSFET conducts for only 20.8% of the switching cycle, while the low-side MOSFET conducts for the remaining 79.2%.

This creates a common engineering trap: most hobbyists buy two identical MOSFETs for the high and low sides. However, because the low-side RMS current is nearly double the high-side RMS current, conduction losses (I² × Rds(on)) will heavily skew toward the low side. To balance thermal dissipation, the low-side MOSFET should have an Rds(on) roughly one-quarter that of the high-side MOSFET.

• Controller: TI LM5117 (Wide Vin synchronous buck controller, rated to 100V, featuring adaptive dead-time control to prevent shoot-through).
• High-Side MOSFET: Infineon BSC060N10NS3 (100V, 6.0 mΩ Rds(on)). Optimized for fast switching to minimize turn-on/off losses during the short 20.8% on-time.
• Low-Side MOSFET: Infineon BSC026N04NS (40V, 2.6 mΩ Rds(on)). The 40V rating is safe because this MOSFET only sees the 5V output voltage plus a small ringing spike when the high-side turns on. The ultra-low Rds(on) handles the 79.2% conduction time.
• Inductor: 4.7 µH shielded ferrite core (e.g., Wurth 7443552470), rated for 15A saturation current.
• Switching Frequency (fsw): 300 kHz (chosen to keep the inductor physically small while avoiding excessive gate-charge switching losses).

Inductor Sizing and Ripple Current Math

We target an inductor ripple current (ΔIL) of 30% of the maximum load current (3A peak-to-peak). The required inductance is calculated as:

L = (Vin - Vout) × D / (fsw × ΔIL)
L = (24 - 5) × 0.208 / (300,000 × 3) = 4.38 µH

We select a standard 4.7 µH inductor. The peak current the inductor and low-side MOSFET must handle is I_load + (ΔIL / 2) = 10A + 1.5A = 11.5A. Ensure your inductor's saturation current (Isat) rating is at least 20% above this 11.5A peak to prevent core saturation and catastrophic MOSFET failure during load transients.

Thermal Derating, Protection, and Ripple Expectations

Designing the schematic is only half the battle; the physical layout determines whether your MOSFET power supply survives a 50°C summer day inside an inverter chassis.

Thermal Derating and PCB Heatsinking

Modern power MOSFETs in SON or DFN packages rely on the PCB copper pour as their primary heatsink. A bare BSC026N04NS in a 5x6mm package has a junction-to-ambient thermal resistance (RθJA) of roughly 50°C/W if mounted on a minimal footprint. At 2W of conduction loss, the junction would rise 100°C above ambient.

To derate this properly, you must use an array of thermal vias (typically 0.3mm diameter, 1mm pitch) directly under the MOSFET's exposed thermal pad, connecting the top copper layer to a solid ground plane on the bottom layer. This drops the effective RθJA to approximately 15°C/W. With 2W dissipated, the junction temperature rises only 30°C above ambient. Always check the manufacturer's thermal derating curves; Infineon's OptiMOS datasheets explicitly chart maximum continuous drain current against ambient temperature for specific PCB copper areas.

Ripple and Noise Expectations

Switching power supplies inherently generate output voltage ripple, driven by two factors: the Equivalent Series Resistance (ESR) of the output capacitors and the capacitive charge/discharge cycle.

For a 10A load with 3A of inductor ripple, the ESR ripple is calculated as ΔV_esr = ΔIL × ESR. If you use standard electrolytic capacitors with an ESR of 20 mΩ, your ripple will be 3A × 0.020Ω = 60 mV. This is unacceptable for sensitive 5V logic and microcontrollers.

The solution is to use a bank of low-ESR Multilayer Ceramic Capacitors (MLCCs) or Polymer capacitors. Three 100 µF, 10V X7R MLCCs in parallel will yield a combined ESR of roughly 1 mΩ.

• ESR Ripple: 3A × 0.001Ω = 3 mV
• Capacitive Ripple: ΔIL / (8 × fsw × C_total) = 3 / (8 × 300,000 × 0.0003) = 4.1 mV
• Total Expected Ripple: ~7.1 mV peak-to-peak.

Be aware of the DC bias effect in ceramic capacitors. A 100 µF X7R 10V capacitor biased at 5V may lose up to 30% of its nominal capacitance. Always select a voltage rating at least double your output voltage (e.g., 10V or 16V rated caps for a 5V rail) to maintain actual capacitance and keep the capacitive ripple component low.

High di/dt Layout Rules

The most critical layout constraint in a MOSFET power supply is the high di/dt (change in current over time) loop. When the high-side MOSFET turns on, current surges from the input capacitors, through the high-side MOSFET, through the inductor, and back via the ground plane. The physical area of this loop must be minimized to reduce parasitic inductance. High parasitic inductance causes severe voltage ringing at the switch node (SW), which can exceed the MOSFET's drain-source breakdown voltage (Vds) and destroy the silicon. Place your input bypass capacitors (a mix of 10 µF MLCC and 100 nF high-frequency ceramic) as physically close to the high-side drain and low-side source pins as the PCB routing allows, utilizing wide, short copper traces rather than long, thin runs.