A hardware boolean circuit evaluates logical states using physical voltage thresholds rather than software instructions. When you need a dual-sensor safety interlock—where a 12V relay must only engage if both a limit switch (Sensor A) and a pressure comparator (Sensor B) are HIGH—relying on a microcontroller introduces boot latency, brownout vulnerabilities, and software bugs. A discrete hardware logic gate provides deterministic, nanosecond-level evaluation. For a robust 12V industrial or automotive interlock, the optimal topology is a CD4081B CMOS AND gate driving an IRLZ44N logic-level MOSFET.
The Core Topology: Node Labels and Signal Flow
Before picking components, we must define the topology and node labels. This boolean circuit operates on a 12V DC supply, translating logical states into physical relay actuation. According to fundamental digital logic principles outlined by All About Circuits, an AND gate outputs a HIGH state only when all inputs are HIGH.
Topology Node Definitions:
- VCC (12V): Main power rail feeding the logic IC and relay coil.
- GND: Common ground reference for logic and power.
- Node A: Input 1 (e.g., Limit Switch, active HIGH).
- Node B: Input 2 (e.g., Pressure Sensor comparator output, active HIGH).
- Node Y: Logic Output (Pin 3 of the AND gate).
- Node G: MOSFET Gate (driven by Node Y through a series resistor).
- Node D: MOSFET Drain (connected to the Relay Coil negative terminal).
- Node S: MOSFET Source (connected to GND).
Decision Path: Selecting the Right Logic Family
Not all logic ICs are created equal. The most common mistake hobbyists make is reaching for the 74HC08 (standard 5V HCMOS) for a 12V system, which requires messy level-shifting or a separate 5V regulator. Below is the decision matrix for selecting your boolean logic IC.
| Condition / Requirement | Recommended Topology | Why This Wins |
|---|---|---|
| 5V logic, <5ns propagation delay needed | 74HC08 | Fast switching, standard TTL/CMOS levels |
| 12V industrial, high noise immunity needed | CD4081B (Default Pick) | Wide VCC (3V-15V), high noise margins, no level shifters |
| Simple, no ICs available in a pinch | Discrete DTL (Diode-Transistor) | Failsafe, but requires 5+ discrete parts per gate |
| Complex state memory or timing required | Microcontroller (e.g., ATtiny85) | Programmable, but introduces boot latency and software risk |
The Concrete Pick: For any 12V sensor interlock, use the CD4081B (e.g., Texas Instruments CD4081BE). It operates natively at 12V, meaning a 12V HIGH input is recognized cleanly, and its 12V HIGH output is more than sufficient to fully enhance a logic-level MOSFET without a gate driver.
Design Walkthrough: Real Component Values
Here is the exact bill of materials and design rationale for the interlock. You can reference the TI CD4081B Datasheet for the internal schematic and electrical characteristics.
- U1 (Logic IC): CD4081B Quad 2-Input AND Gate. Tie unused inputs (pins 8, 9, 12, 13) to GND to prevent floating-node oscillation and excess current draw.
- R1, R2 (Input Pull-downs): 100kΩ resistors from Node A to GND, and Node B to GND. If a sensor wire breaks, these force the inputs LOW, ensuring a fail-safe relay drop-out.
- R3 (Gate Series Resistor): 470Ω between Node Y and Node G. This limits the inrush current into the MOSFET gate capacitance and protects the CD4081B output stage if the gate shorts to ground.
- R4 (Gate Pull-down): 10kΩ from Node G to GND. This ensures the MOSFET stays OFF during the brief moment the CD4081B is powering up and its outputs are undefined.
- Q1 (MOSFET): IRLZ44N. It has a Vgs(th) of 1-2V and an Rds(on) of 22mΩ at 5V. At 12V gate drive, it will easily handle a 5A relay coil without a heatsink.
- D1 (Flyback Diode): 1N4007 placed in reverse bias across the relay coil (Cathode to 12V, Anode to Node D). This clamps the inductive kickback when the MOSFET switches off, preventing voltage spikes from destroying Q1.
Behavior Matrix and Extreme Failure Modes
A robust design must account for what happens when things break. Below is the truth table combined with extreme fault analysis.
| Input A | Input B | Node Y (Logic) | MOSFET State | Relay State |
|---|---|---|---|---|
| 0V (Low) | 0V (Low) | 0V | Cutoff | De-energized |
| 12V (High) | 0V (Low) | 0V | Cutoff | De-energized |
| 0V (Low) | 12V (High) | 0V | Cutoff | De-energized |
| 12V (High) | 12V (High) | ~11.5V | Saturation (ON) | Energized |
What Breaks at the Extremes?
Scenario 1: Input A wire breaks (Open Circuit).
Because of the 100kΩ pull-down (R1), Node A is pulled to 0V. The boolean AND condition fails. Node Y goes LOW, the MOSFET turns off, and the relay drops out. Result: Fail-safe.
Scenario 2: Node Y shorts directly to GND.
The CD4081B attempts to source current. At 12V, the IC can source roughly 6.8mA. The 470Ω series resistor (R3) limits this current, preventing the IC from overheating. The 10kΩ gate pull-down (R4) keeps Node G at 0V. Result: Relay stays off, IC survives.
Scenario 3: Node G (MOSFET Gate) shorts to VCC (12V).
This bypasses the logic entirely. The MOSFET turns on hard, and the relay energizes regardless of sensor states. Result: Fail-dangerous. This is the inherent limitation of single-channel hardware logic. For life-safety applications (like a press brake or elevator), you must use dual-channel redundancy or a certified safety PLC to detect shorts to VCC.
Step-by-Step Breadboard Testing Protocol
Do not just plug it in and hope. Follow this exact verification sequence to prevent bricking your IC or popping your MOSFET.
- Visual and Continuity Check (Power OFF): Set your multimeter to continuity mode. Place one probe on the VCC rail and the other on the GND rail. You should read an open circuit (OL). If it beeps, you have a short—likely a misaligned IC or a stray wire strand. Fix it before proceeding.
- Verify Pull-downs: Measure resistance from Node A to GND, and Node B to GND. Both should read exactly 100kΩ (±5%). This confirms your fail-safe pull-downs are physically connected.
- Apply Logic Power Only: Connect a bench power supply set to 12.0V to VCC and GND. Leave the 12V relay coil disconnected for now. Measure the voltage at Pin 14 (VCC) and Pin 7 (GND) of the CD4081B to confirm the IC is receiving power.
- Test the Boolean Logic: Leave Inputs A and B unconnected (floating). Measure Node Y (Pin 3). It should read 0V (the 100k pull-downs are working). Now, use a jumper wire to briefly touch Node A to 12V. Node Y should remain 0V. Touch both Node A and Node B to 12V simultaneously. Node Y should immediately jump to ~11.5V.
- Verify MOSFET Turn-Off: Remove the 12V jumpers. Measure Node G. It should read 0V, confirming the 10kΩ pull-down (R4) is actively draining the gate capacitance and keeping the MOSFET off during logic transitions.
- Connect the Load: Power down. Wire the relay coil between 12V and Node D. Ensure the 1N4007 flyback diode is oriented correctly (stripe facing 12V). Power up and repeat the dual-input trigger. You should hear the relay click, and measuring across the coil should show 12V.
By strictly adhering to the CD4081B topology with the specified pull-down and series resistors, you eliminate the floating-node oscillation and inductive kickback failures that plague amateur hardware logic designs. For any 12V combinatorial interlock where software latency is unacceptable, this exact component lineup is the definitive standard.
