A robust power supply switching schematic for a 24V-to-5V/3A battery or solar bus requires a synchronous buck topology, input TVS protection, and low-ESR ceramic output filtering to keep ripple under 30mV. When stepping down from a nominal 24V lead-acid or LiFePO4 battery bank to power embedded controllers or logic rails, linear regulators will literally melt under the heat load, making a switched-mode design mandatory. This guide breaks down the exact topology selection, component values, and thermal derating math you need to draft a reliable schematic for off-grid and mobile power systems.

Topology Selection: Linear vs. Switching for Your Load

The first decision in any power supply switching schematic is choosing between linear and switching topologies. For low-current, noise-sensitive analog front-ends (like a 20mA sensor bias rail), a linear low-dropout regulator (LDO) is ideal due to its microvolt-level noise floor. However, for a 24V nominal battery system stepping down to a 5V logic rail at 3A, linear regulation is physically unviable.

Consider the dropout and headroom math for a linear regulator: dropping 24V to 5V at 3A results in a power dissipation of 57 Watts (P = (24V - 5V) × 3A). A standard TO-220 packaged LDO maxes out around 2W of dissipation without an impractical, massive heatsink. Switching to a buck converter operating at 88% efficiency reduces that heat dissipation to roughly 2W, which can be easily managed with a standard PCB copper pour.

Power Supply Topology Comparison for 24V Battery Systems (15W Output Load)
Topology Typical Efficiency Heat Dissipation Output Noise Relative BOM Cost
Linear (LDO) ~21% 57.0 W < 1 mV RMS $0.50 - $1.50
Asynchronous Buck 75% - 85% 2.6 W - 5.0 W 20 - 50 mV p-p $2.00 - $4.00
Synchronous Buck 88% - 95% 0.8 W - 2.0 W 15 - 40 mV p-p $3.50 - $6.00
SEPIC (Non-inverting) 80% - 88% 2.0 W - 3.7 W 30 - 60 mV p-p $5.00 - $8.00

For our 24V-to-5V application, the synchronous buck is the clear winner. It replaces the catch diode found in asynchronous designs with a second internal MOSFET, eliminating the diode's forward voltage drop and significantly improving efficiency at high currents.

Anatomy of a 24V-to-5V Buck Power Supply Switching Schematic

Designing the schematic requires more than just dropping a regulator IC onto the page. A 24V nominal battery bus is a hostile electrical environment. During absorption charging, a 24V lead-acid bank can reach 28.8V, and inductive load dumps from motors or relays can spike the bus well past 35V. Your input stage must handle this range and protect the downstream switching node.

Input Protection and UVLO

Never connect a switching regulator directly to a battery bus without transient protection. The schematic must include:

  • TVS Diode: An SMAJ33A (33V standoff, 53.3V clamp) absorbs high-energy inductive spikes before they breach the IC's absolute maximum input rating.
  • Reverse Polarity Protection: Use a P-channel MOSFET (like the SI2301) instead of a series Schottky diode. A Schottky will drop 0.4V to 0.6V, wasting power and generating heat. A PMOS drops only millivolts based on its Rds(on).
  • UVLO (Under-Voltage Lockout): Most modern ICs have this built-in via an EN (enable) pin resistor divider. Set the UVLO threshold to 18V to prevent the converter from attempting to regulate when the battery is deeply discharged, which could cause excessive input current draw.

Regulator Selection and Passives

For this design, we will use the Texas Instruments LMR14030, a 40V, 3.5A synchronous buck converter with an integrated high-side and low-side MOSFET. It operates at a fixed 500kHz switching frequency, allowing for a compact inductor footprint.

LMR14030 24V-to-5V Schematic Component Values
Parameter Calculated / Selected Value Component Selection Notes
Inductor (L) 10 µH Shielded ferrite, >4.5A saturation current. Calculated for 30% ripple current at 28.8V max input.
Output Capacitance (Cout) 3 × 47 µF (141 µF total) X7R dielectric MLCCs, 10V rated. Low ESR minimizes output voltage ripple.
Input Capacitance (Cin) 2 × 10 µF + 1 × 0.1 µF X7R MLCCs placed as close to the VIN and PGND pins as physically possible.
Bootstrap Capacitor (Cboot) 0.1 µF X7R, 16V rated. Required to drive the high-side gate above the input rail.
Feedback Divider (Rfbt / Rfbb) 100kΩ / 31.6kΩ Sets output to 5.0V based on the IC's 0.8V internal reference. Use 1% tolerance.

Ripple and Noise Expectations

In a switching schematic, output ripple is dominated by the inductor ripple current flowing through the equivalent series resistance (ESR) of the output capacitors. The formula is ΔV_out = ΔI_L × ESR. By using three parallel 47µF X7R ceramic capacitors, the combined ESR drops to roughly 2mΩ. With a 0.9A inductor ripple current, the ESR-induced ripple is a negligible 1.8mV. The remaining ripple (typically 15mV to 25mV peak-to-peak) is driven by the capacitors' equivalent series inductance (ESL) and the physical layout loop area. If your load is a sensitive RF module or a high-resolution ADC, add a small ferrite bead and a secondary LC pi-filter stage after the main buck output to push noise below 5mV.

Thermal Derating, Dropout, and Headroom Math

Selecting the right IC is only half the battle; verifying that it won't thermally throttle or drop out of regulation under edge-case battery voltages is what separates a hobbyist schematic from a production-ready design.

Dropout and Minimum On-Time Headroom

Switching regulators are constrained by their minimum on-time (t_on_min). The LMR14030 has a t_on_min of 130ns. At a 500kHz switching frequency (2000ns period), the maximum duty cycle is limited to 93.5%. If the battery voltage sags during a heavy motor start, the converter must increase its duty cycle to maintain 5V. The minimum input voltage required to maintain regulation without pulse-skipping is calculated as:

V_in_min = V_out / D_max
V_in_min = 5.0V / 0.935 = 5.34V

Since a 24V battery system will trigger the UVLO shutdown at 18V, we have massive headroom. The converter will never approach dropout conditions unless the battery is essentially dead.

Thermal Derating and PCB Heat Sinking

Let's calculate the junction temperature at maximum load. At 5V and 3A (15W output), operating at 89% efficiency, the total power dissipated by the IC and inductor is roughly 1.85W. The LMR14030 comes in a SOIC-8 package with an exposed thermal pad. According to the TI buck converter design guidelines, when mounted on a 4-layer PCB with a 2oz copper pour on the bottom layer acting as a heatsink, the junction-to-ambient thermal resistance (θ_JA) drops to approximately 32°C/W.

The temperature rise above ambient is:

ΔT = P_dissipated × θ_JA
ΔT = 1.85W × 32°C/W = 59.2°C

If this power supply is mounted inside an inverter enclosure where the ambient air reaches 45°C on a hot summer day, the silicon junction temperature will be 104.2°C (45°C + 59.2°C). This is well below the 150°C thermal shutdown threshold, but it leaves only a 45°C safety margin. If your enclosure lacks ventilation, you must either lower the switching frequency (reducing switching losses at the cost of a larger inductor) or add forced air cooling.

PCB Layout Warning: Never route high-di/dt switching node (SW) traces under the feedback (FB) resistor divider. The rapid dV/dt noise from the inductor switching will capacitively couple into the high-impedance FB trace, causing erratic PWM duty cycles and severe output voltage oscillation. Keep the SW node copper area as small as possible to minimize EMI radiation, and route the FB trace directly from the output capacitor back to the IC pin, shielded by ground planes on adjacent layers.

For deeper insights into calculating inductor saturation margins and selecting the right switch-mode topology for complex battery paths, refer to the Analog Devices topology selection guide. By anchoring your power supply switching schematic in hard thermal math and strict input protection rules, you ensure your 24V system survives the harsh reality of off-grid power environments.