If you are pushing switching frequencies past 500 kHz or trying to shrink the magnetics in a 48V datacenter power supply, silicon MOSFETs will bottleneck your design. The GaN HEMT transistor (Gallium Nitride High Electron Mobility Transistor) solves this by offering near-zero reverse recovery charge ($Q_{rr}$), dramatically lower gate charge ($Q_g$), and a fraction of the on-resistance ($R_{DS(on)}$) of equivalent silicon parts. But GaN is not a drop-in replacement for silicon. Its gate oxide is fragile, its threshold voltage is low, and its switching speeds will ring your PCB traces into oscillation if layout and biasing are ignored.
This guide strips away the semiconductor physics and focuses entirely on what you need at the workbench: how to read the pinout, how to bias it without blowing the gate, a complete reference circuit, and how to test a suspected dead part with your multimeter.
Symbol, Pinout, and Safe Default Part Numbers
Unlike vertical silicon MOSFETs, most commercial GaN HEMTs are lateral devices. This means the Drain, Source, and Gate are all located on the same side of the die. In modern chip-scale packages (like LGA or BGA), the pins are replaced by solder pads on the bottom of the component.
When selecting a part, you must match the voltage rating to your bus voltage with at least a 20% derating margin, and ensure the package can handle your thermal load. Here are three safe default part numbers for common topologies in 2026:
| Part Number | Manufacturer | $V_{DS}$ Rating | $R_{DS(on)}$ | Continuous Current | Best Application |
|---|---|---|---|---|---|
| EPC2045 | EPC | 100V | 7 mΩ | 16A | 48V to 12V Buck, LiDAR pulsers |
| GS61008P | GaN Systems | 100V | 7 mΩ | 90A | High-current 48V server power |
| IGT60R070D1 | Infineon | 600V | 70 mΩ | 8.3A | AC/DC PFC, Class-D audio amps |
Operation Regions and Biasing Selection
Biasing a GaN HEMT transistor requires a fundamental mindset shift from silicon. The gate threshold voltage ($V_{th}$) is typically around 1.2V to 1.7V, compared to 3V–5V for silicon. More critically, the absolute maximum gate-to-source voltage ($V_{GS}$) is usually just 6V or 7V. Pushing a standard 12V silicon gate drive signal into a GaN gate will instantly puncture the gate dielectric and destroy the part.
Here is how the device behaves across its operating regions, which dictates how you design your gate driver:
| Region | Bias Condition | Typical Voltages (100V Class) | Behavior in Circuit |
|---|---|---|---|
| Cutoff | $V_{GS} < V_{th}$ | $V_{GS} = 0V$, $V_{DS} = 48V$ | Device is OFF. Only leakage current flows. |
| Linear (Ohmic) | $V_{GS} > V_{th}$, $V_{DS} < V_{GS} - V_{th}$ | $V_{GS} = 5V$, $V_{DS} = 0.5V$ | Acts as a low-value resistor ($R_{DS(on)}$). Used for synchronous rectification. |
| Saturation | $V_{GS} > V_{th}$, $V_{DS} \ge V_{GS} - V_{th}$ | $V_{GS} = 5V$, $V_{DS} = 10V$ | Current is constant, controlled by $V_{GS}$. Used in linear amplifiers (rare for power GaN). |
Application Circuit: 48V to 12V Synchronous Buck Converter
To see these biasing rules in action, let us look at a complete, buildable 1 MHz synchronous buck converter stepping 48V down to 12V at 10A. This topology relies heavily on the GaN HEMT transistor's lack of reverse recovery to maintain high efficiency at 1 MHz.
Bill of Materials (BOM)
- Q1 (High-Side) & Q2 (Low-Side): EPC2045 (100V, 7mΩ GaN FETs)
- U1 (Gate Driver): LMG1210 (Half-bridge driver with adjustable dead-time)
- L1 (Inductor): 1.5 µH, shielded ferrite core, rated for 15A saturation (e.g., Coilcraft XEL series)
- C_OUT (Output Caps): 4x 47µF, 25V X7R MLCC (1206 package)
- C_IN (Input Caps): 2x 10µF, 100V X7R MLCC placed within 2mm of Q1 Drain and Q2 Source
- C_BOOT (Bootstrap Cap): 100nF, 16V X7R (Low ESR required)
- R_G1, R_G2 (Gate Resistors): 2.2Ω (0402 package, placed as close to the gate pad as possible to damp high-frequency ringing)
Build and Layout Steps
- Establish the High-Frequency Loop: Route the 100V input capacitors directly to the Drain of Q1 and the Source of Q2. This loop carries the highest $di/dt$ in the circuit. Keep it under 5mm in total length using 2oz copper on the top layer.
- Place the Gate Drivers: Mount U1 (LMG1210) directly adjacent to Q1 and Q2. The gate traces must be short, wide, and run over a solid ground plane to minimize gate loop inductance.
- Implement Thermal Vias: GaN chip-scale packages dissipate heat through the PCB. Place an array of 0.3mm vias directly under the Source and Drain pads of the EPC2045s, stitching to a solid copper pour on the bottom layer.
- Set Dead-Time: Program the LMG1210 dead-time to 10ns. Because GaN has no body diode, excessive dead-time forces the inductor current through the 'third quadrant' channel of the low-side FET, which has a higher voltage drop (~1.3V) and wastes power.
Failure Modes and Multimeter Testing
When a prototype board fails, you need to know if the GaN HEMT transistor is dead and why it died. GaN devices fail differently than silicon.
Common Failure Mechanisms
- Gate Oxide Puncture: Caused by exceeding $V_{GS(max)}$ (usually 6V-7V). This results in a hard short between Gate and Source.
- Miller Turn-On ($dv/dt$ induced): When the high-side FET switches on, the massive voltage spike ($dv/dt$) on the switch-node couples through the low-side FET's $C_{gd}$ (Miller capacitance), momentarily spiking its gate voltage above $V_{th}$. Both FETs conduct simultaneously, causing a shoot-through short that melts the die.
- Thermal Runaway: Inadequate PCB thermal vias cause the die temperature to spike, increasing $R_{DS(on)}$ and leading to a cascading thermal failure.
How to Test with a Digital Multimeter
You cannot test a GaN FET exactly like a silicon MOSFET because there is no body diode. Set your multimeter to Diode Test Mode.
- Test Drain-to-Source (D-S): Place the red probe on Drain, black on Source. It should read 'OL' (Open Loop). Reverse the probes. It should also read 'OL'. (If you see a 0.4V - 0.6V drop in one direction, you are either testing a silicon MOSFET, or your GaN FET has an integrated diode/silicon cascode, which is rare for modern discrete lateral GaN).
- Test Gate-to-Source (G-S): Place probes across Gate and Source in both directions. It must read 'OL'. If it reads 0.00V or beeps (short circuit), the gate oxide is punctured. The part is dead.
- Test Gate-to-Drain (G-D): Place probes across Gate and Drain in both directions. It must read 'OL'. A short here indicates internal die destruction.
- Charge the Gate (Functional Check): With the multimeter in resistance mode, briefly touch the positive lead to the Gate and negative to the Source to inject a tiny charge. Switch back to Diode mode and measure D-S; you may see a brief low reading before it floats back to OL as the charge dissipates.
Frequently Asked Questions
Can I drive a GaN HEMT transistor directly with a standard 12V silicon MOSFET gate driver?
No. Doing so will almost certainly destroy the device on the first switching cycle. Standard silicon MOSFET drivers output 10V to 12V to fully enhance the channel. A GaN HEMT transistor is fully enhanced at 5V, and its absolute maximum gate-to-source voltage rating is typically 6V or 7V. Exceeding this limit punctures the ultra-thin gate dielectric instantly. You must use a dedicated GaN gate driver IC with tightly regulated output voltages, or clamp the gate with a fast 5.1V Zener diode and a series gate resistor.
Why does my GaN HEMT transistor keep turning on by itself during high-side switching?
This is known as Miller turn-on or $dv/dt$ induced turn-on. Because GaN FETs switch incredibly fast (high $dv/dt$) and have a low gate threshold voltage ($V_{th} \approx 1.3V$), the rapid voltage rise on the switch node couples through the Miller capacitance ($C_{gd}$) into the gate of the low-side FET. If the gate turn-off impedance is too high, this coupled current spikes the gate voltage above $V_{th}$, causing shoot-through. To fix this, use a gate driver with a strong pull-down (sink) current, minimize the physical distance between the driver and the GaN gate pad, or utilize a driver that offers a negative turn-off bias (e.g., pulling the gate to -2V during the off-state).
Do GaN HEMT transistors have a body diode for synchronous rectification?
No, lateral GaN HEMTs do not have a physical P-N junction body diode, meaning they have absolutely zero reverse recovery charge ($Q_{rr} = 0$). However, they can conduct current in the reverse direction (from Source to Drain) when the gate is off and the drain-to-source voltage exceeds a specific threshold (typically around 1.3V to 1.5V). This is known as 'third quadrant operation' where the 2DEG channel acts as a pseudo-diode. Because this forward voltage drop (1.3V) is much higher than a silicon diode's 0.7V, it causes significant conduction losses if left active for too long. You must minimize the dead-time in your gate driver to ensure the low-side FET's gate is turned on (shorting the channel and dropping the voltage to $I \times R_{DS(on)}$) as quickly as possible.
