The Capacitor Series Formula: When and Why to Wire in Series

The capacitor series formula dictates that the total equivalent capacitance ($C_{eq}$) of capacitors wired in series is the reciprocal of the sum of their individual reciprocals. For two capacitors, the shortcut is:

$C_{eq} = (C_1 \times C_2) / (C_1 + C_2)$

If you are wiring three or more, the full formula is $1/C_{eq} = 1/C_1 + 1/C_2 + 1/C_3 + ...$ You can explore the foundational physics of this inverse relationship on the Georgia State University HyperPhysics reference.

Why use this topology when it actively reduces your total capacitance? You wire capacitors in series when your circuit's operating voltage exceeds the maximum Working Voltage DC (WVDC) rating of a single, readily available component. By stacking them, you divide the voltage stress across multiple dielectrics. While parallel wiring adds capacitance, series wiring multiplies voltage handling. This is standard practice in high-voltage DC bus snubbers, tube amplifier power supplies, and resonant induction heating tanks.

Topology, Node Labels, and the Balancing Act

A basic two-capacitor series string consists of three distinct nodes:

  • Node A (HV+): The high-voltage input, connected to the positive lead of Capacitor 1.
  • Node B (Midpoint): The junction where the negative lead of Capacitor 1 meets the positive lead of Capacitor 2.
  • Node C (HV- / Return): The ground or return path, connected to the negative lead of Capacitor 2.
Safety Warning: High-voltage DC is lethal and does not trigger standard AC breakers easily. Never build or test series capacitor banks at voltages above 50V on a standard solderless breadboard. Arcing across the plastic dividers will destroy the board and pose a severe shock hazard. Always use perfboard, dead-bug wiring, or a proper PCB, and always include a high-wattage bleeder resistor to discharge the bank when power is removed.

The Balancing Act: In a perfect world, two identical 630V capacitors in series across an 800V bus would each drop exactly 400V. In reality, differences in leakage current and dielectric absorption cause the voltage to divide unequally. One capacitor might see 550V while the other sees 250V, leading to overvoltage failure of the first. To force equal DC voltage sharing, you must wire high-value balancing resistors in parallel with each capacitor.

Series vs. Parallel: Failure Modes and Extremes

Understanding what happens when a component fails is critical for topology selection. Here is how a series string behaves at the extremes compared to a parallel bank.

Event Series Topology Result Parallel Topology Result
C1 Opens Circuit breaks entirely. Total capacitance drops to zero. The HV bus loses its snubber/filter. Total capacitance drops by the value of C1. Circuit continues to operate at reduced capacity.
C1 Shorts Node A and Node B merge. The full bus voltage dumps instantly across C2. If C2 WVDC is exceeded, it vents or explodes. Dead short across the entire power supply. Blows the main fuse or trips the breaker immediately.
C1 Drifts (Ages) Voltage division shifts. The aging capacitor takes on a higher share of the DC voltage stress, accelerating its own death. Minimal impact. Total capacitance drops slightly, but voltage rating of the bank remains intact.

For deeper reading on how series and parallel configurations affect total circuit impedance and transient response, the Electronics Tutorials capacitor series guide provides excellent AC frequency domain analysis.

Design Walkthrough: 800V DC Bus Snubber Bank

Let us design a snubber for an 800V DC link in a solar inverter. We need roughly 0.5µF of capacitance to absorb high-frequency switching spikes from the SiC MOSFETs. Single 1200V, 0.5µF film capacitors are physically massive and cost upwards of $45 each. Instead, we will use the capacitor series formula to build a bank from standard, cheaper components.

Component Selection:

  • Capacitors: Two 1.0µF, 630VDC WIMA MKP10 polypropylene film capacitors (approx. $4.50 each).
  • Target $C_{eq}$: $(1.0 \times 1.0) / (1.0 + 1.0) = 0.5\mu F$.
  • Theoretical Voltage Rating: $630V + 630V = 1260V$. Derated for safety margins and transient spikes, this safely handles our 800V DC bus.

Calculating Balancing Resistors:

We need to bleed off leakage current to ensure the 800V splits into two 400V drops. A standard rule of thumb for film capacitors is to use resistors that draw roughly 1mA to 2mA at the maximum bus voltage.

  • Resistance Value: $R = V_{total} / I_{bleed} = 800V / 0.002A = 400k\Omega$ total. Since they are in series across the supply, we use two 220kΩ resistors (yielding 440kΩ total).
  • Current: $800V / 440k\Omega = 1.81mA$.
  • Power Dissipation per Resistor: $P = I^2 \times R = (0.00181)^2 \times 220,000 = 0.72W$.
  • Physical Part: We select 220kΩ, 2-Watt metal film resistors (e.g., Vishay PR02 series) to provide a safe thermal margin above the 0.72W calculated dissipation.
Bench Tip: When wiring the balancing resistors, do not just solder them to the capacitor leads at the very tip. Bend the resistor leads and wrap them around the capacitor leads before soldering to maximize mechanical strength, especially if the assembly will be subjected to vibration in an industrial enclosure.

Step-by-Step Bench Testing Protocol

Do not connect this assembly to the 800V bus until you have verified the voltage division at a safe, low-voltage bench level. Follow this exact sequence:

  1. Visual and DMM Check: With the circuit unpowered, use a multimeter in resistance mode to verify the 220kΩ resistors are reading correctly (±5%). Verify there are no solder bridges between Node A, B, and C.
  2. LCR Meter Validation: Connect an LCR meter across Node A and Node C. Set the test frequency to 1kHz. The meter should read 0.5µF (±10% tolerance for the WIMA MKP10 series). If it reads 1.0µF, you have accidentally wired them in parallel.
  3. Low-Voltage Power Up: Connect a benchtop DC power supply across Node A (positive) and Node C (negative). Set the supply to 50.0V and current limit to 50mA.
  4. Midpoint Measurement: Using a high-impedance digital multimeter, measure the DC voltage from Node B to Node C. You should read exactly 25.0V (±0.5V). If Node B reads 40V and Node C reads 10V, your balancing resistors are faulty or mismatched.
  5. Thermal Check: Leave the 50V applied for 15 minutes. Touch the resistors. They should be barely warm. (At 50V, dissipation is only ~2.8mW per resistor; they will only get hot at the full 800V operating point).

Decision Tree: Selecting Your Capacitor Topology

Use this decision matrix to terminate your design process with a concrete topology choice. Do not default to series wiring just because you have extra capacitors in your bin; the failure modes are strictly worse than parallel or single-component designs.

Design Condition Action / Topology Pick Concrete Example
Bus voltage is lower than a single capacitor's WVDC rating. Use a Single Capacitor. Avoid unnecessary points of failure. 12V circuit needing 100µF: Use one 100µF 25V electrolytic.
Bus voltage is safe, but you need more capacitance or lower ESR. Wire in Parallel. Capacitance adds; voltage rating stays at the lowest component's rating. 5V logic rail needing low noise: Parallel four 0.1µF MLCCs.
Bus voltage exceeds the WVDC of available, reasonably priced capacitors. Wire in Series. Add balancing resistors. Calculate $C_{eq}$ to ensure you still meet the minimum required capacitance. 400V tube amp B+ rail: Series two 220µF 250V electrolytics with 100kΩ balancers.
You need both higher voltage handling AND higher capacitance. Series-Parallel Matrix. Build series strings first, then wire those strings in parallel. 800V DC link needing 2.0µF: Build four strings of two 1.0µF 630V caps, then parallel the strings.

By strictly applying the capacitor series formula and respecting the physical realities of leakage current and voltage derating, you can reliably design high-voltage banks that survive the harsh transients of modern power electronics. Always prioritize the balancing resistors—they are the only thing standing between a stable DC midpoint and a catastrophic dielectric puncture.