The fundamental electrical formula for capacitance is C = Q / V, which defines capacitance (C) as the ratio of stored electric charge (Q) to the voltage (V) across the component. When designing physical components or analyzing PCB parasitics, the geometric formula C = (ε₀ · εᵣ · A) / d is used to calculate capacitance based on plate area, separation distance, and dielectric material.
Below, we break down every symbol, explore the assumptions that make these formulas valid, and walk through real-world bench calculations with strict unit tracking.
The Core Formulas for Capacitance and Symbol Definitions
Capacitance can be approached from two angles: the electrical behavior in a circuit, and the physical geometry of the component. Both are critical for a complete understanding.
| Symbol | Parameter | SI Unit | Common Bench Units |
|---|---|---|---|
| C | Capacitance | Farad (F) | μF, nF, pF |
| Q | Electric Charge | Coulomb (C) | mC, μC |
| V | Voltage (Potential Difference) | Volt (V) | V, mV |
| ε₀ | Vacuum Permittivity | F/m | 8.854 × 10⁻¹² F/m (Constant) |
| εᵣ | Relative Permittivity (Dielectric Constant) | Dimensionless | Air ≈ 1.0, FR4 ≈ 4.5, X7R ≈ 2000+ |
| A | Area of Overlapping Plates | Square Meter (m²) | cm², mm² |
| d | Distance Between Plates (Dielectric Thickness) | Meter (m) | mm, μm |
Rearranged Forms
On the bench, you rarely solve for C directly. You usually know your capacitance and need to find the voltage rating, charge capacity, or physical dimensions. Here are the rearranged forms:
- Solving for Charge: Q = C × V
- Solving for Voltage: V = Q / C
- Solving for Plate Area: A = (C × d) / (ε₀ × εᵣ)
- Solving for Dielectric Thickness: d = (ε₀ × εᵣ × A) / C
- Solving for Dielectric Constant: εᵣ = (C × d) / (ε₀ × A)
Assumptions, Magnitudes, and Unit Traps
When the Formula Applies (And Its Assumptions)
The geometric formula C = (ε₀ · εᵣ · A) / d assumes a uniform electric field between two perfectly parallel, infinitely wide plates. In reality, fringing fields at the edges of the plates slightly increase the actual capacitance. For most hobbyist and commercial PCB traces or discrete components where the plate area is vastly larger than the separation distance (A >> d²), this edge effect is negligible. It also assumes a linear dielectric, meaning εᵣ remains constant regardless of the applied voltage. (Note: Class II ceramic capacitors like X5R/X7R violate this assumption heavily, losing up to 50% of their nominal capacitance at rated DC bias).
Realistic Answer Magnitudes
If your calculation yields a result outside these typical ranges, check your decimal places:
- 1 pF to 10 pF: Parasitic trace capacitance, RF tuning circuits.
- 100 pF to 1 nF: High-frequency decoupling, crystal oscillator load caps.
- 10 nF to 1 μF: Standard digital IC decoupling, audio coupling.
- 10 μF to 10,000 μF: Bulk power supply filtering, motor snubbers.
- 1 F to 3,000 F: Supercapacitors for memory backup or regenerative braking.
Which Unit Mistakes Break the Math
The most common bench failure is the area conversion trap. When converting mm² to m², you must multiply by 10⁻⁶, not 10⁻³. Similarly, converting cm² to m² requires multiplying by 10⁻⁴. A second fatal error is mixing microfarads (μF) with Coulombs without applying the 10⁻⁶ scaling factor, resulting in voltage calculations that are off by a factor of a million.
Worked Problem 1: Charge Storage in a DC Filter Bank
Scenario: You are designing a linear power supply and need to know how much charge is stored in your bulk filter capacitor to ensure it can ride through a brief mains dropout. You have a 470 μF electrolytic capacitor charged to 24 V DC.
- Identify the knowns and target:
C = 470 μF
V = 24 V
Target: Q (Charge in Coulombs) - Convert to base SI units:
C = 470 × 10⁻⁶ F = 0.00047 F
V = 24 V (already in base units) - Select the rearranged formula:
Q = C × V - Substitute and calculate:
Q = (470 × 10⁻⁶ F) × (24 V)
Q = 11,280 × 10⁻⁶ C
Q = 0.01128 C - Convert to practical bench units:
Q = 11.28 mC (millicoulombs)
Bench Takeaway: 11.28 mC seems small, but if your circuit draws a steady 50 mA (0.05 A), this charge can sustain the load for t = Q / I = 0.01128 / 0.05 = 0.225 seconds (225 ms) before the voltage drops to zero, assuming an ideal linear discharge.
Worked Problem 2: Physical Geometry of a DIY Parallel Plate
Scenario: You are experimenting with high-voltage RF and decide to build a simple parallel plate capacitor using a piece of double-sided copper-clad FR4 PCB material. The copper squares are 50 mm × 50 mm, and the FR4 core thickness is 1.6 mm. The relative permittivity (εᵣ) of FR4 at RF frequencies is approximately 4.5.
- Identify the knowns:
ε₀ = 8.854 × 10⁻¹² F/m
εᵣ = 4.5
A = 50 mm × 50 mm
d = 1.6 mm - Convert to base SI units (The Danger Zone):
A = 0.05 m × 0.05 m = 0.0025 m² (or 2500 mm² × 10⁻⁶ = 0.0025 m²)
d = 1.6 × 10⁻³ m = 0.0016 m - Select the geometric formula:
C = (ε₀ × εᵣ × A) / d - Substitute and calculate:
C = (8.854 × 10⁻¹² × 4.5 × 0.0025) / 0.0016
C = (9.96075 × 10⁻¹¹) / 0.0016
C = 6.225 × 10⁻¹¹ F - Convert to practical bench units:
C = 62.25 × 10⁻¹² F = 62.25 pF
Bench Takeaway: This 62 pF parasitic capacitance is negligible for a 60 Hz power supply, but if this PCB is used in a 100 MHz RF amplifier, that 62 pF will act as a low-impedance short to ground (Xc = 1 / (2πfC) ≈ 25 Ω), completely killing your signal. Always calculate PCB pad parasitics using this geometric formula.
Real-World Scenario: The ESP32 Brownout and Decoupling Failure
Formulas don't exist in a vacuum; they dictate whether your embedded system runs or crashes. Here is a real-world troubleshooting scenario where misapplying capacitance concepts led to a field failure.
The Setup
An engineering team designed a battery-powered IoT sensor using an ESP32-WROOM-32 module. During WiFi transmission bursts, the module experienced random brownout resets. The 3.3V LDO regulator was rated for 600 mA, which should have been plenty.
The Numbers
According to the Espressif datasheet, a WiFi TX burst draws a peak current (I) of 240 mA for a duration (Δt) of roughly 2 ms. The ESP32's brownout detector triggers if the VDD33 rail drops below 3.0V. Therefore, the maximum allowable voltage droop (ΔV) from the nominal 3.3V is 0.3 V.
We use the transient capacitance formula derived from I = C(dV/dt):
C = (I × Δt) / ΔV
- Convert to base units:
I = 0.24 A
Δt = 0.002 s
ΔV = 0.3 V - Calculate required bulk capacitance:
C = (0.24 × 0.002) / 0.3
C = 0.00048 / 0.3
C = 0.0016 F = 1.6 mF (1600 μF)
The Outcome and What Went Wrong
The original schematic featured a single 100 μF ceramic capacitor near the ESP32. The designer assumed 100 μF was 'large enough' for digital decoupling. When the 240 mA hit, the 100 μF capacitor drained in less than 0.15 ms, causing the rail to plummet past the 3.0V threshold, triggering a brownout reset.
However, simply slapping a 2200 μF electrolytic capacitor on the board didn't fix it immediately. Why? Equivalent Series Resistance (ESR) and trace inductance. A standard 2200 μF aluminum electrolytic capacitor might have an ESR of 0.5 Ω. When 240 mA flows through that ESR, Ohm's law dictates an instantaneous voltage drop of V = I × R = 0.24 A × 0.5 Ω = 0.12 V before the capacitive discharge even begins.
The Fix: The team replaced the 100 μF cap with a parallel bank consisting of a 2200 μF low-ESR polymer capacitor (ESR < 0.015 Ω) to supply the bulk charge, paired with a 100 nF X7R ceramic capacitor placed within 2 mm of the ESP32 VDD pins to handle the high-frequency nanosecond switching edges. The geometric formula dictated the physical placement (minimizing 'd' and 'A' of the current loop to reduce parasitic inductance), while the electrical formula dictated the bulk value. For a deeper dive into placement strategies, refer to Analog Devices' guidelines on bypass capacitors.
