An FGMOS (Floating-Gate MOSFET) transistor is not a discrete power switch you drop onto a breadboard to drive a motor or switch a relay. It is a specialized MOSFET featuring an electrically isolated polysilicon gate designed to trap electrical charge for years without power. This charge-trapping mechanism is the physical foundation of all modern non-volatile memory (Flash, EEPROM) and programmable analog ICs (digital potentiometers, FPAAs).

If you are searching for a bare, 3-pin discrete FGMOS to switch a 12V load, you will not find one. Instead, hardware designers interact with FGMOS structures embedded inside integrated circuits. This guide bridges the gap between semiconductor physics and bench-level practice, showing you how FGMOS devices operate, how to emulate and test their charge-injection behavior on a workbench, and exactly which FGMOS-based ICs to select for your next design.

Symbol, Pinout, and the 'Missing' Gate Connection

To understand how to bias an FGMOS, you must first look at its schematic symbol and physical pinout. Unlike a standard enhancement-mode MOSFET with a single gate terminal, the FGMOS features two distinct gate structures:

  • Control Gate (CG): The external terminal you actually connect to your circuit. It receives the read, program, or erase voltages.
  • Floating Gate (FG): A secondary polysilicon layer buried entirely within the silicon dioxide ($SiO_2$) insulation. It has no direct electrical connection to any external pin.
  • Drain (D), Source (S), and Bulk (B): Standard MOSFET terminals. The channel forms between the Drain and Source, directly beneath the Floating Gate.
Bench Insight: Because the Floating Gate is capacitively coupled to the Control Gate, the actual voltage driving the channel ($V_{FG}$) is a weighted average of the Control Gate voltage ($V_{CG}$) and the charge trapped on the floating gate ($Q_{FG}$). The formula is: $V_{FG} = (C_{CG} / C_{total}) imes V_{CG} + (Q_{FG} / C_{total})$. This is why programming an FGMOS literally shifts its threshold voltage ($V_{th}$).

Operation Regions and Threshold Voltage Shifts

An FGMOS operates in the exact same Cut-off, Linear, and Saturation regions as a standard MOSFET. The critical difference is that the threshold voltage ($V_{th}$) is not a fixed factory constant; it is a variable determined by the trapped charge. When electrons are forced onto the floating gate via Fowler-Nordheim (FN) tunneling, they create an opposing electric field, effectively raising the $V_{th}$ required to turn the transistor on.

FGMOS Operation Regions and Typical Biasing Voltages
Region Condition (N-Channel) Typical Read Voltage ($V_{CG}$) Typical Program Voltage ($V_{CG}$) Physical State of Floating Gate
Cut-off $V_{CG} < V_{th(shifted)}$ 0V - 1.5V 10V - 15V (FN Tunneling) Electrons trapped on FG; channel pinched off.
Linear (Ohmic) $V_{CG} > V_{th(shifted)}$ and $V_{DS} < V_{GS} - V_{th}$ 3.3V - 5.0V N/A (Avoid during programming) FG discharged (Erased); acts as a closed switch.
Saturation $V_{CG} > V_{th(shifted)}$ and $V_{DS} \ge V_{GS} - V_{th}$ 3.3V - 5.0V N/A FG discharged; acts as a constant current source.

In a commercial EEPROM like the Microchip AT24C256, an 'Erased' cell (no charge on FG) has a low $V_{th}$ (e.g., 1.5V) and turns ON when read at 3.3V, representing a logic '1'. A 'Programmed' cell (electrons on FG) has a high $V_{th}$ (e.g., 4.5V) and stays OFF when read at 3.3V, representing a logic '0'.

Application Circuit: Bench-Emulated FGMOS Charge Injection

Since you cannot purchase a discrete FGMOS transistor, semiconductor students and analog designers use a 'macro-model' circuit to emulate FGMOS charge injection and threshold shifting on a standard breadboard. This circuit allows you to visualize Fowler-Nordheim tunneling and measure the resulting $V_{th}$ shift using standard bench equipment.

Component List

  • Q1: 2N7000 (Standard N-Channel MOSFET, acts as the base channel)
  • C_fg: 10pF Ceramic Capacitor (Simulates the oxide capacitance between CG and FG)
  • R_tunnel: 100MΩ Resistor (Simulates the high-impedance tunneling oxide)
  • U1: LM358 Dual Op-Amp (Configured as a current-to-voltage sense amplifier)
  • R_sense: 10Ω Shunt Resistor
  • V_prog: 15V Pulse Source (Simulates the high-voltage charge pump)
  • V_read: 5V DC Source (Standard logic read voltage)

Wiring and Numbered Steps

  1. Build the Floating Gate Node: Connect the 10pF capacitor ($C_{fg}$) in series with the Gate of the 2N7000. The junction between the capacitor and the MOSFET gate is your emulated 'Floating Gate' node.
  2. Add the Tunneling Path: Connect the 100MΩ resistor ($R_{tunnel}$) from the 15V Pulse Source ($V_{prog}$) to the Floating Gate node. This high resistance mimics the quantum tunneling barrier that only conducts under high electric fields.
  3. Connect the Control Gate: Apply your 5V Read signal ($V_{read}$) to the free leg of the 10pF capacitor. This is your Control Gate input.
  4. Wire the Sense Amplifier: Connect the Source of the 2N7000 to ground through the 10Ω shunt resistor ($R_{sense}$). Wire the non-inverting input of the LM358 to the Source side of the shunt, and the inverting input to ground. Set the op-amp gain to 10x using standard feedback resistors (e.g., $R_f = 90k\Omega$, $R_i = 10k\Omega$).
  5. Execute the 'Program' Pulse: Apply a 100ms, 15V pulse to $V_{prog}$. Current will leak through the 100MΩ resistor, charging the 10pF capacitor. This emulates electrons tunneling onto the floating gate.
  6. Execute the 'Read' Phase: Remove the 15V pulse. Apply 5V to the Control Gate ($V_{read}$). Observe the LM358 output. Because the 10pF capacitor is now charged, it opposes the 5V Control Gate signal, lowering the effective $V_{GS}$ of the 2N7000. The drain current will drop significantly compared to the un-programmed state, proving the $V_{th}$ has shifted.
Design Note: In actual silicon FPAAs (Field Programmable Analog Arrays), this exact capacitive divider principle is used to program analog current mirrors. By trapping precise amounts of charge on the floating gate, designers can trim transistor mismatch errors down to microvolt levels.

Failure Modes and Multimeter Testing

Testing an FGMOS is fundamentally different from testing a standard MOSFET. A standard multimeter diode test will only check the body diode between the Drain and Source. It cannot detect the state of the Floating Gate because there is no DC path to it. Furthermore, FGMOS devices suffer from unique failure modes related to their ultra-thin tunneling oxides (often less than 10nm thick).

FGMOS Failure Modes and Diagnostic Procedures
Failure Mode Physical Cause Symptom in Circuit How to Test / Diagnose
Oxide Punch-Through Overvoltage during programming ruptures the $SiO_2$ tunneling layer. Cell becomes permanently stuck in one state (cannot be erased or reprogrammed). Attempt a full Erase/Program cycle via the IC's host controller. If the data byte refuses to flip, the oxide is breached.
Charge Leakage (Retention) Microscopic defects in the oxide allow trapped electrons to slowly leak off the FG over years. EEPROM/Flash data corruption after prolonged storage or high-temperature exposure. Read the memory array and compare against a known checksum. Marginal cells will show up as bit-flips.
Read Disturb Repeatedly applying the read voltage causes slight, cumulative hot-carrier injection into the FG. Cells adjacent to frequently read addresses slowly shift their $V_{th}$ and eventually flip states. Monitor the $V_{th}$ distribution margin using specialized memory controller diagnostic commands (e.g., S.M.A.R.T. data on SSDs).

Testing a Discrete RADFET (FGMOS Sensor) with a Multimeter

There is one niche exception where you can buy a discrete FGMOS-like device: the RADFET (Radiation-sensing FET), such as the REMOS REM-01. These are essentially p-channel MOSFETs with a specialized floating gate/oxide designed to trap charge when exposed to ionizing radiation.

To test a RADFET with a bench multimeter and a variable power supply:

  1. Set your multimeter to measure current (mA) and place it in series with the Drain.
  2. Ground the Source and Bulk.
  3. Sweep the Gate voltage ($V_{GS}$) from 0V to -5V using a variable supply.
  4. Record the exact $V_{GS}$ where the Drain current reaches 100µA. This is your current $V_{th}$.
  5. Compare this value to the factory calibration sheet. A negative shift in $V_{th}$ directly correlates to the absorbed radiation dose (measured in Rads).

Decision Path: Selecting FGMOS-Based Components

Because the FGMOS is an internal building block rather than a standalone discrete component, 'selecting an FGMOS' actually means selecting the right IC architecture that utilizes FGMOS arrays for your specific application. Use the decision matrix below to terminate your component search with a concrete, safe default part number.

FGMOS IC Selection Decision Matrix
If your application requires... Then you need this FGMOS architecture... Safe Default Part Number & Ratings
Non-volatile data logging, configuration storage, or MAC address retention. Serial EEPROM (Pure FGMOS array optimized for 1M+ write cycles and 100-year retention). Microchip AT24C256C
Rating: 256Kbit, I2C, 1.7V-5.5V, 1M write cycles.
Trimming an analog sensor offset, setting a bias current, or calibrating a gain stage that must survive power loss. Non-Volatile Digital Potentiometer (FGMOS cells store the wiper position in analog voltage steps). Microchip MCP4551-104E/P
Rating: 100kΩ, I2C, 257-step, 2.7V-5.5V.
Measuring cumulative ionizing radiation dose in a medical, aerospace, or nuclear environment. RADFET Dosimeter (Discrete FGMOS with radiation-sensitive gate oxide). REMOS REM-01
Rating: P-Channel, 0 to 100 kRad(Si) range, TO-18 package.
Prototyping complex programmable analog filters, oscillators, or PID controllers without discrete passives. FPAA (Field Programmable Analog Array) (FGMOS transistors used to program continuous-time analog signal paths). Anadigm AN221E04
Rating: 4x4 CAM array, 2.7V-3.6V, SPI interface.

The Concrete Default Pick for Bench Prototyping

If you are a hobbyist or student looking to experiment with FGMOS charge-trapping principles in an analog circuit without designing custom silicon, the Microchip MCP4551-104E/P is your definitive starting point. Priced around $1.50 in single quantities, it operates on standard 5V I2C logic, requires no high-voltage charge pumps (the internal FGMOS programming circuitry is handled by the IC's onboard state machine), and allows you to build non-volatile, programmable current sources and voltage dividers that retain their exact state after a power outage. Wire its wiper to the non-inverting input of an LM358 op-amp, and you instantly have a programmable, FGMOS-backed analog bias generator.