When you write embedded C code for an Arduino or ESP32, the compiler handles the math. But when you are debugging a motor encoder that suddenly rolls over from 127 to -128, or analyzing a core dump from a crashed RTOS task, you need to understand what the Arithmetic Logic Unit (ALU) is actually doing at the silicon level. Microcontrollers do not have dedicated subtraction circuits; they rely entirely on addition and bitwise inversion.

This guide walks through a classic digital electronics exam problem. By working through this example of binary subtraction, you will see exactly how hardware executes signed math, where the common traps lie, and how to verify your results on the bench.

The Problem Statement: 8-Bit Signed Subtraction

📝 EXAM PROBLEM

Calculate 42 - 58 using 8-bit signed two's complement binary arithmetic.

  1. Show the binary representation of both operands.
  2. Perform the subtraction using the appropriate binary theorem.
  3. State the final 8-bit binary result and its decimal equivalent.
  4. Identify the status of the Carry and Overflow flags.

Step-by-Step Solution: Applying Two's Complement

Which method applies and why? We use the Two's Complement Addition method. In digital logic, the ALU performs subtraction by converting the subtrahend (the number being subtracted) into its negative two's complement form, and then adding it to the minuend. The governing theorem is: A - B = A + (~B + 1), where ~B is the bitwise NOT (one's complement) of B. This allows the hardware to use a single adder circuit for both addition and subtraction, saving silicon area and power.

Step 1: Convert the Minuend (42) to 8-Bit Binary

We find the binary weightings for 42 (64, 32, 16, 8, 4, 2, 1):

  • 42 = 32 + 8 + 2
  • Binary: 00101010

Step 2: Convert the Subtrahend (58) to 8-Bit Binary

Find the binary weightings for 58:

  • 58 = 32 + 16 + 8 + 2
  • Binary: 00111010

Step 3: Calculate the Two's Complement of 58 (to get -58)

First, find the One's Complement by inverting every bit (0 becomes 1, 1 becomes 0):

  • Original (58): 00111010
  • Inverted (~58): 11000101

Next, add 1 to the One's Complement to get the Two's Complement:

  11000101  (One's complement)
+ 00000001  (Add 1)
----------
  11000110  (Two's complement = -58)

Step 4: Add 42 and -58

Now we perform standard binary addition. We must track the carry bit for every column, as this is critical for determining the microcontroller's status flags later.

Carries:  01111000
          --------
   42:    00101010
+ (-58):  11000110
          --------
Result:   11110000

Algebraic breakdown of the addition (Right to Left, LSB to MSB):

  • Bit 0: 0 + 0 = 0 (Carry 0)
  • Bit 1: 1 + 1 = 0 (Carry 1)
  • Bit 2: 0 + 1 + 1(carry) = 0 (Carry 1)
  • Bit 3: 1 + 0 + 1(carry) = 0 (Carry 1)
  • Bit 4: 0 + 0 + 1(carry) = 1 (Carry 0)
  • Bit 5: 1 + 0 + 0(carry) = 1 (Carry 0)
  • Bit 6: 0 + 1 + 0(carry) = 1 (Carry 0)
  • Bit 7 (MSB): 0 + 1 + 0(carry) = 1 (Carry Out = 0)

The final 8-bit result is 11110000.

The Trap: Carry-Out vs. Overflow

⚠️ THE EXAM TRAP

The most common mistake students make in this example of binary math is confusing the Carry flag (C) with the Overflow flag (V).

In our addition, the carry-out from the MSB (Bit 7) was 0. In unsigned arithmetic, a carry-out indicates an overflow. However, we are doing signed arithmetic. In signed two's complement, the Carry flag is ignored for overflow detection. Instead, the Overflow flag is triggered if the carry into the MSB differs from the carry out of the MSB.

  • Carry into Bit 7: 0
  • Carry out of Bit 7: 0
  • 0 XOR 0 = 0 (No Overflow)

Furthermore, a signed overflow can only occur when adding two numbers of the same sign. Since we added a positive number (42) and a negative number (-58), it is mathematically impossible to exceed the 8-bit signed range (-128 to +127). The ALU's Overflow flag remains clear.

Answer Sanity Check and Independent Verification

How do you verify the answer independently without relying on a calculator? You reverse the two's complement process to map the binary result back to a human-readable decimal magnitude.

  1. Check the MSB: The result is 11110000. The Most Significant Bit (Bit 7) is 1, which dictates that this is a negative number in signed representation.
  2. Find the Magnitude: Take the two's complement of the result to find its absolute value.
    • Invert 11110000 → 00001111
    • Add 1 → 00010000
  3. Convert to Decimal: 00010000 has a single 1 in the 16's place (Bit 4). The magnitude is 16.
  4. Apply the Sign: Since the MSB was 1, the final decimal value is -16.

Sanity Check: Does 42 - 58 = -16? Yes. The order of magnitude is correct, the sign is correct, and the binary perfectly maps to the expected decimal algebra. For a deeper dive into how microcontrollers handle these specific status register flags (like the SREG in AVR chips), refer to the binary arithmetic chapters on All About Circuits or the Two's Complement guides on Electronics Tutorials.

FAQ: Common Questions About Binary Examples

What is the most common example of binary in microcontrollers?

The most frequent real-world example of binary math in microcontrollers is handling quadrature encoder counts for motor control. Encoders output pulses that are counted in hardware timer registers. When a motor reverses direction, the register must subtract counts. If the register is 8-bit and the count drops below 0, it relies on two's complement to wrap around to 255 (which represents -1 in signed 8-bit math). If your firmware treats this register as an unsigned integer instead of a signed integer, your PID control loop will see a massive sudden spike in position, causing the motor to violently overcorrect.

How do you represent fractional numbers in an example of binary math?

Standard two's complement handles integers. To represent fractions, embedded systems use fixed-point arithmetic or the IEEE 754 floating-point standard. In a fixed-point example of binary, you designate a specific number of bits for the fractional part. For instance, in an 8-bit Q4.4 format, the top 4 bits are the signed integer, and the bottom 4 bits are the fraction (representing halves, quarters, eighths, and sixteenths). The binary 0001.1000 would equal 1.5 (1 + 1/2). This is heavily used in audio DSPs and older Cortex-M0 microcontrollers that lack a hardware Floating Point Unit (FPU).

Why does my example of binary addition drop the last carry bit?

In an 8-bit ALU, there are only 8 physical flip-flops to store the result of an operation. If an addition generates a 9th bit (the carry-out), it has nowhere to go in the primary register. The hardware routes this 9th bit directly into the Carry Flag (C) in the status register. In unsigned math, you must check this flag to detect overflow. In signed two's complement math, the carry-out is mathematically irrelevant to the final value and is intentionally ignored by the CPU when evaluating the signed result, which is why our 11110000 result is perfectly valid despite the internal bitwise carries.