An electronics LDO (Low Dropout Regulator) is a linear DC-DC converter that maintains a stable output voltage even when the input voltage is dangerously close to the target output. The direct answer: Choose an LDO when your load current is under 300mA, your input-to-output differential ($V_{in} - V_{out}$) is less than 2V, and your circuit demands ultra-low noise (like RF transceivers, precision ADCs, or audio DACs). If you need to drop 12V to 3.3V at 1A, put the LDO away and grab a switching buck converter.
In this guide, we will break down the exact math for dropout voltage and thermal derating, compare topologies, and walk through a real-world design example using industry-standard parts.
LDO vs. Switching Regulator: The Topology Showdown
When designing a power tree, the first decision is linear vs. switching for your specific load. A switching buck converter stores energy in an inductor and releases it in pulses, achieving high efficiency but generating electromagnetic interference (EMI) and switching ripple. An electronics LDO acts as a smart, variable resistor, burning off excess voltage as heat to deliver a perfectly clean DC rail.
| Feature | Electronics LDO (Linear) | Switching Buck Converter |
|---|---|---|
| Efficiency | Poor ($V_{out} / V_{in}$). E.g., 3.3V/5V = 66% | High (85% - 95% typical) |
| Heat Dissipation | High ($P_D = \Delta V \times I_{load}$) | Low (losses mainly in MOSFETs/inductor DCR) |
| Output Noise | Ultra-low (nV/√Hz), no switching ripple | High (mV-level switching ripple at kHz/MHz) |
| Cost & BOM | Low ($0.10 - $0.50, requires 2 caps) | Medium ($1.00+, inductor, diode, boot cap) |
| Design Complexity | Trivial (plug and play) | Moderate (requires loop compensation/layout care) |
When to choose which: Use an electronics LDO for post-regulation (cleaning up a noisy switching rail for an analog sensor), low-current MCU rails (ESP32 deep sleep), or battery-powered wearables where quiescent current ($I_Q$) matters more than raw efficiency. Use a switcher for high-current digital loads, FPGAs, or when $V_{in}$ is significantly higher than $V_{out}$.
Design Example: Dropout Math and Thermal Derating
Let's design a 3.3V rail from a 5V USB supply to power an MCU and a few I2C sensors. Our maximum expected load is 250mA.
Part Selection and Dropout Headroom
We select the Microchip MCP1700-3302E/TO, a classic 250mA electronics LDO in a SOT-23 package. The datasheet specifies a maximum dropout voltage ($V_{dropout}$) of 178mV at 250mA.
Our nominal headroom is $5.0V - 3.3V = 1.7V$ (1700mV). We have 1522mV of margin. Even if the USB port sags to 4.0V under heavy host loading, our headroom drops to 700mV, which is still well above the 178mV dropout threshold. The regulator will maintain a clean 3.3V output.
Thermal Math and Derating
Linear regulators dissipate the voltage difference as heat. The power dissipation ($P_D$) formula is:
$P_D = (V_{in} - V_{out}) \times I_{load}$
$P_D = (5.0V - 3.3V) \times 0.25A = 0.425W$
To find the junction temperature ($T_J$), we use the thermal resistance from junction to ambient ($\theta_{JA}$) for the SOT-23 package, which is roughly 150 °C/W on a standard PCB with minimal copper pour.
$\Delta T = P_D \times \theta_{JA} = 0.425W \times 150°C/W = 63.75°C$
At a 25°C room ambient, $T_J = 25°C + 63.75°C = 88.75°C$. The absolute maximum $T_J$ is 125°C, so the part is technically safe. However, the silicon will be too hot to touch, and efficiency is a mediocre 66%.
Input Protection, Ripple, and Noise Expectations
An electronics LDO provides a clean output, but it is not invincible. Understanding its input limitations and noise rejection capabilities is critical for a robust design.
Input Range and Protection
Most low-cost LDOs have strict absolute maximum input voltage ratings. The MCP1700, for example, maxes out at 6.0V. If you connect it directly to a 12V automotive battery or a 9V wall adapter, a load dump or voltage spike will instantly destroy the silicon, potentially passing the full input voltage to your 3.3V MCU and frying it.
Protection Strategy: Always place a TVS (Transient Voltage Suppression) diode (like the SMAJ5.0A) on the input to clamp spikes, and use a P-channel MOSFET for reverse-polarity protection. If your input source is highly inductive, add a bulk electrolytic capacitor (e.g., 47µF) near the input to absorb cable-ring transients.
Ripple and Noise Expectations (PSRR)
LDOs do not generate switching ripple, but they do not magically erase noise present on the input rail. Their ability to reject input noise is defined by the Power Supply Rejection Ratio (PSRR), measured in decibels (dB).
According to Texas Instruments' linear regulator design guidelines, a typical LDO might offer 60dB of PSRR at 1kHz, meaning it attenuates input ripple by a factor of 1000. However, as frequency increases into the MHz range (where switching regulators operate), PSRR often degrades to 20dB or less due to internal parasitic capacitances.
The Fix: To maintain high-frequency noise rejection, always use a high-quality, low-ESR X7R ceramic capacitor (typically 1µF to 4.7µF) directly on the output pin. This capacitor acts as a low-impedance shunt for high-frequency noise that the LDO's internal feedback loop is too slow to correct.
Frequently Asked Questions
What is the difference between a standard linear regulator and an electronics LDO?
Standard linear regulators (like the legendary LM317 or LM7805) use NPN Darlington pass transistors, which require 2V to 3V of headroom (dropout voltage) to remain in regulation. An electronics LDO uses a P-channel MOSFET or PNP transistor as the pass element, allowing the dropout voltage to shrink to under 200mV. This makes LDOs ideal for battery-powered devices where every millivolt of battery capacity counts.
How do I calculate the required heatsink for an LDO in a high-current circuit?
For through-hole packages like the TO-220, you calculate the required heatsink thermal resistance ($R_{\theta SA}$) using the formula: $R_{\theta SA} = (T_{J(max)} - T_{A}) / P_D - (\theta_{JC} + \theta_{CS})$, where $\theta_{JC}$ is junction-to-case and $\theta_{CS}$ is case-to-sink (thermal paste). However, modern surface-mount electronics LDOs (SOT-23, DFN, WSON) do not use physical heatsinks. Instead, you must rely on PCB thermal vias and large internal ground-plane copper pours to spread the heat, effectively lowering the $\theta_{JA}$ of the board itself.
Why does my LDO oscillate or output the wrong voltage on the breadboard?
This is almost always a capacitor Equivalent Series Resistance (ESR) issue. Older LDO architectures (like the LM1117) require a minimum ESR (often 0.1Ω to 1Ω) on the output capacitor to introduce a zero in the feedback loop and maintain phase margin. If you use a modern, ultra-low-ESR ceramic capacitor with an older LDO, the loop becomes unstable and oscillates. Conversely, modern electronics LDOs (like the TLV757P or MCP1700) are internally compensated specifically for low-ESR ceramics. Always check the datasheet's "Output Capacitor Requirements" graph before swapping cap types.
Can I use an electronics LDO to step up voltage or regulate a negative rail?
No LDO can step up (boost) voltage; the input must always be higher than the output by at least the dropout voltage. For negative rails (e.g., generating -5V for an op-amp from a -12V rail), you cannot use a standard positive LDO. You must select a dedicated negative-voltage LDO (like the TPS7A30 or LM7905), where the input pin is tied to the more negative voltage, and the output provides the regulated, less-negative rail relative to the system ground.
