A NOT gate (inverter) flips a logic HIGH to LOW and vice versa. While you can easily grab a 74HC04 hex inverter IC for a few cents, building a discrete NOT logic gate circuit diagram from scratch teaches you the foundational physics of digital switching. In modern IoT and custom sensor design, discrete inverters are still used to interface mismatched voltage domains or drive loads that would fry a standard CMOS IC.
We will use a standard NPN BJT (2N3904) to build a 5V logic inverter, calculate the exact resistor values for deep saturation, and map out the failure modes. The direct answer for a standard 5V TTL-compatible inverter: use a 2N3904 NPN transistor with a 4.7 kΩ base resistor and a 1.0 kΩ collector pull-up resistor.
The Discrete NOT Logic Gate Circuit Diagram & Topology
The topology of a BJT inverter is a common-emitter switch. Unlike an integrated CMOS inverter which uses complementary P-channel and N-channel MOSFETs to actively drive the output both high and low, this discrete design uses a passive pull-up resistor and an active pull-down transistor.
Here is the topology mapped to specific node labels:
- Node A (Input / $V_{IN}$): The control signal (0V or 5V) fed into the base resistor.
- Node B (Base Junction): The connection between the base resistor and the transistor base pin.
- Node C (Output / $V_{OUT}$): The collector pin, tied to VCC via the pull-up resistor. This is where the inverted logic is read.
- Node D (Emitter / Ground): The emitter pin, tied directly to the system ground (0V).
Why This Topology Over the Alternative?
Why use a discrete BJT instead of a discrete MOSFET (like a 2N7000) or a standard 74HC04 IC? A 74HC04 is limited to roughly 25mA of output drive current and strict 5V/3.3V rails. A discrete BJT like the 2N3904 can sink up to 200mA, allowing the inverter to directly drive relays, high-current LEDs, or indicator lamps. Compared to a small-signal MOSFET, the BJT offers a sharper, more predictable saturation voltage ($V_{CE(sat)}$) at low currents, guaranteeing a solid logic LOW (under 0.3V) without the gate-threshold variability inherent to cheap MOSFETs.
Component Selection & Design Walkthrough
To ensure the transistor acts as a switch and not a linear amplifier, we must drive it into deep saturation. This requires calculating an overdrive factor for the base current. Below is the spec-sheet-table for a 5V system driving a standard logic input or a 10mA LED load.
| Component | Part Number / Type | Value | Purpose & Calculation |
|---|---|---|---|
| Q1 (Switch) | 2N3904 (NPN BJT) | N/A | $h_{FE}$ (gain) min 100. $V_{CE(sat)}$ typically 0.2V at 10mA. |
| R_B (Base) | Carbon Film 1/4W | 4.7 kΩ | Limits base current. $I_B = (5V - 0.7V) / 4700Ω = 0.91mA$. |
| R_C (Collector) | Carbon Film 1/4W | 1.0 kΩ | Pull-up resistor. Limits max $I_C$ to $(5V - 0.2V) / 1000Ω = 4.8mA$. |
| VCC | Bench Supply | 5.0 V DC | Standard TTL logic level supply. Tolerance ±5%. |
The Saturation Math
For Q1 to saturate, the base current ($I_B$) must be high enough to support the collector current ($I_C$). With a 1.0 kΩ collector resistor, the maximum $I_C$ is roughly 4.8mA. Assuming a conservative minimum DC current gain ($h_{FE}$) of 100 (per the Onsemi 2N3904 datasheet), the absolute minimum base current required is $4.8mA / 100 = 0.048mA$.
By using a 4.7 kΩ base resistor, we supply 0.91mA of base current. This gives us an overdrive factor of roughly 19 ($0.91mA / 0.048mA$). This massive overdrive guarantees the transistor slams fully into saturation, pulling Node C down to $V_{CE(sat)}$ (about 0.1V to 0.2V), which registers as a definitive logic LOW to any downstream 5V TTL or CMOS input.
Behavior Matrix & Extreme Failure Modes
Understanding how the circuit behaves under normal conditions is only half the battle. As noted in All About Circuits' semiconductor guide, analyzing failure modes is critical for robust design. Below is the normal behavior matrix, followed by what breaks at the extremes.
| Input State (Node A) | Q1 State | Output State (Node C) | Current Draw from VCC |
|---|---|---|---|
| LOW (0V) | Cutoff (Open) | HIGH (~5.0V) | ~0 mA (negligible leakage) |
| HIGH (5V) | Saturation (Closed) | LOW (~0.2V) | ~4.8 mA (through R_C and Q1) |
What Breaks at the Extremes?
Digital logic is unforgiving when passive components fail. Here is the failure-mode contrast for this specific topology:
- Shorted R_B (Base Resistor): If the 4.7 kΩ resistor shorts, Node A connects directly to the base-emitter junction. The base current spikes to $(5V - 0.7V) / 0Ω$, limited only by the power supply's internal resistance and the silicon's bulk resistance. This will instantly exceed the 2N3904's absolute maximum continuous base current (typically 50mA), melting the base-emitter junction and destroying the transistor.
- Open R_C (Collector Resistor): If the pull-up resistor breaks open, the inverter loses its ability to drive a HIGH signal. When Q1 turns off, Node C enters a high-impedance (high-Z) floating state. It will read random noise on a multimeter and cause erratic behavior in downstream logic gates.
- Shorted Q1 (Collector-to-Emitter): If the transistor fails short, Node C is permanently tied to ground. The output is stuck at a logic LOW (0V) regardless of the input, and R_C will continuously dissipate $25mW$ ($5V^2 / 1000Ω$), which is well within its 1/4W rating, so the resistor will survive.
Remember that a 5V CMOS gate (like the TI SN74HC04) requires a HIGH input to be at least 70% of VCC (3.5V). When your discrete NOT gate outputs HIGH (Node A = 0V), Node C will sit at 5.0V, easily clearing the 3.5V threshold. When it outputs LOW, it sits at 0.2V, well below the 1.5V maximum LOW threshold.
Step-by-Step Breadboard Testing Procedure
Do not just wire this blindly. Follow this exact sequence to verify the discrete NOT logic gate circuit diagram on a standard 830-point solderless breadboard.
- De-energize and Prep: Ensure your bench power supply is OFF and disconnected from the breadboard rails. Set the supply to 5.0V and current limit to 100mA to protect against accidental shorts.
- Place Q1: Insert the 2N3904 into the breadboard. Critical: With the flat side facing you, the pins from left to right are Emitter (E), Base (B), and Collector (C). Ensure each pin is in a separate row.
- Wire the Emitter (Node D): Run a jumper from the Emitter pin to the negative (ground) rail.
- Install R_C (Pull-up): Insert the 1.0 kΩ resistor. Connect one end to the Collector pin (Node C) and the other end to the positive (5V) rail.
- Install R_B (Base Drive): Insert the 4.7 kΩ resistor. Connect one end to the Base pin (Node B) and leave the other end exposed in an empty row to serve as your Input (Node A).
- Connect Power: Connect your power supply to the positive and negative rails. Turn the supply ON.
- Test State 1 (Input LOW): Use a jumper wire to connect Node A (the open end of R_B) to Ground. Set your multimeter to DC Voltage. Probe Node C (the Collector). Expected Reading: 4.9V to 5.0V (Logic HIGH).
- Test State 2 (Input HIGH): Move the Node A jumper from Ground to the 5V rail. Probe Node C again. Expected Reading: 0.1V to 0.3V (Logic LOW). If you read > 0.5V, your transistor is not saturating; check your resistor values or transistor pinout.
BJT vs. MOSFET Inverter Topologies
While the 2N3904 BJT is excellent for general-purpose 5V inversion, modern designs often pivot to small-signal MOSFETs like the 2N7000. Here is how the two discrete topologies compare when designing an inverter stage.
| Criteria | BJT Topology (2N3904) | MOSFET Topology (2N7000) |
|---|---|---|
| Input Impedance | Low (Draws ~0.9mA continuously when HIGH) | Extremely High (Draws ~0mA steady state, only gate charge current) |
| Drive Current Capability | High (Up to 200mA continuous collector current) | Moderate (Typically 200mA to 400mA, but $R_{DS(on)}$ causes heating) |
| Output LOW Voltage | $V_{CE(sat)}$ ~0.2V (Very consistent) | Depends on $I_D \times R_{DS(on)}$ (Can vary with load and temperature) |
| Switching Speed | Slower (Subject to base charge storage time) | Faster (Majority carrier device, no storage delay) |
Decision Framework: Which Should You Choose?
Choose the BJT topology when: You are interfacing with legacy TTL circuits that require strict, predictable low-state voltages, or when you need to sink a heavy, steady DC load (like a 12V relay coil) where the BJT's linear current gain makes base resistor calculation straightforward.
Choose the MOSFET topology when: Your input signal is incredibly weak (like a high-impedance piezo sensor or a microcontroller GPIO pin that cannot spare 1mA of drive current), or when you are switching high-frequency PWM signals where the BJT's base storage time would cause unacceptable edge smearing and switching losses.
Building this discrete NOT gate bridges the gap between abstract Boolean logic and real-world semiconductor physics. By calculating the overdrive factor and understanding the exact failure modes of the pull-up and base resistors, you ensure your custom logic stages will survive the jobsite, not just the simulator.
