De Morgan's law for boolean algebra states that the complement of a logical conjunction (AND) is equivalent to the disjunction (OR) of their complements, and vice versa. In practical electronics, this theorem is the bridge that allows engineers to swap AND/OR gates for NAND/NOR gates, handle active-low signals, and reduce the physical chip count on a printed circuit board. Whether you are writing Verilog for an FPGA, programming ladder logic for an Allen-Bradley PLC, or wiring discrete 7400-series ICs on a breadboard, De Morgan's theorems dictate how you manipulate inverted logic without altering the circuit's fundamental truth table.
The Core Rules and Logic Equivalencies
Augustus De Morgan formalized these rules in the 19th century, but for modern circuit design, they are best understood as 'bubble pushing'—the technique of moving inversion bubbles across logic gates while flipping the gate type. The two primary theorems are:
- Break the bar, change the sign:
NOT (A AND B) = (NOT A) OR (NOT B) - Break the bar, change the sign:
NOT (A OR B) = (NOT A) AND (NOT B)
When applying these rules to physical silicon, you are usually translating between standard gates and their 'universal' counterparts (NAND and NOR). The table below maps the boolean expressions to their physical gate equivalents, including typical propagation delays for standard 5V CMOS logic (e.g., Texas Instruments SN74HC series at 25°C).
| Original Expression | De Morgan Equivalent | Standard Gate Implementation | Equivalent Gate Implementation | Typical Prop Delay (74HC @ 5V) |
|---|---|---|---|---|
NOT (A AND B) |
(NOT A) OR (NOT B) |
NAND Gate | OR Gate with inverted inputs | ~12 ns |
NOT (A OR B) |
(NOT A) AND (NOT B) |
NOR Gate | AND Gate with inverted inputs | ~14 ns |
NOT (NOT A AND NOT B) |
A OR B |
AND Gate with inverted inputs | OR Gate | ~18 ns (AND + INV) |
NOT (NOT A OR NOT B) |
A AND B |
OR Gate with inverted inputs | AND Gate | ~16 ns (OR + INV) |
Worked Example: Optimizing a Discrete Logic BOM
To see what De Morgan's law changes in a real circuit, let us evaluate a 4-input safety interlock function and calculate the physical hardware required to build it.
The Requirement: We need to implement the function Y = NOT ((A AND B) OR (C AND D)). This is an AND-OR-Invert (AOI) function. Let us first evaluate the logic state for a specific binary input: A=1, B=1, C=0, D=1.
- Original Evaluation: (1 AND 1) = 1. (0 AND 1) = 0. (1 OR 0) = 1. NOT(1) = 0.
- Apply De Morgan's Law: Break the main inversion bar and change the OR to an AND. The expression becomes:
Y = NOT(A AND B) AND NOT(C AND D). - Equivalent Evaluation: NOT(1 AND 1) = 0. NOT(0 AND 1) = 1. (0 AND 1) = 0. The output matches perfectly.
Hardware and Timing Impact:
If we build the original expression using discrete 2-input 74HC08 (AND), 74HC32 (OR), and 74HC04 (NOT) ICs, the signal must pass through three stages: AND → OR → NOT. This requires 4 discrete gates and incurs a cumulative propagation delay of approximately 30 ns (10ns + 12ns + 8ns). Furthermore, you must populate three separate IC packages on the PCB, even if you only use one gate from each.
If we build the De Morgan equivalent expression, the function becomes two NAND gates feeding into an AND gate. Using 74HC00 (NAND) and 74HC08 (AND) ICs, the signal passes through only two stages: NAND → AND. This requires only 3 discrete gates and reduces the propagation delay to 22 ns (12ns + 10ns). By applying the theorem, you eliminate an entire IC from the Bill of Materials (BOM), reduce PCB routing complexity, and speed up the circuit by 8 nanoseconds.
Where You Meet De Morgan's Law in Practice
You rarely sit down with a pen and paper to apply De Morgan's theorems manually in modern design; instead, the law is baked into the tools and environments you use daily.
PLC Ladder Logic and Safety Circuits
In industrial automation, physical emergency stop (E-stop) buttons are wired using Normally Closed (NC) contacts so that a broken wire triggers a safe shutdown. When mapping these physical NC contacts into PLC ladder logic (like on a Rockwell MicroLogix or Siemens S7-1200), the logic appears inverted. If a safety relay requires three E-stops to be 'closed' (safe) to run a motor, the physical NC contacts read as TRUE (1) when safe. De Morgan's law allows the programmer to convert a messy rung of parallel normally-open contacts into a clean series of normally-closed contacts, ensuring the software logic perfectly mirrors the physical fail-safe wiring.
FPGA Synthesis and Verilog/VHDL
When writing RTL (Register Transfer Level) code for FPGAs like the Lattice iCE40 or Xilinx Artix-7, synthesis tools aggressively optimize logic. However, writing clean code helps the tool map logic to Look-Up Tables (LUTs) efficiently. Microcontroller and memory interfaces heavily use active-low signals (e.g., CHIP_SELECT_n, WRITE_ENABLE_n). If you need to trigger an action when either Chip Select or Write Enable is inactive, you might write if (~CS_n || ~WE_n). The synthesis tool uses De Morgan's law to map this directly to a single NAND gate inside the FPGA fabric, rather than wasting LUT resources on discrete inverters feeding an OR gate.
Microcontroller GPIO Interrupts
When configuring external interrupts on an ESP32 or STM32, you often deal with active-low interrupt pins from peripherals like the MCP23017 I/O expander. If your firmware logic requires a flag to be set when both INT_A and INT_B are pulled low, applying De Morgan's law in your C/C++ bitwise operations prevents inverted logic bugs that typically cause peripheral lockups during initialization.
Common Pitfalls and Troubleshooting Logic Errors
What do people commonly confuse De Morgan's Law with?
The most frequent error is confusing De Morgan's theorems with the Distributive Law. The Distributive Law states that A AND (B OR C) = (A AND B) OR (A AND C). Notice that there are no inversion bars (NOT operators) being broken or moved. Beginners often attempt to 'distribute' a NOT sign across an AND gate without changing the AND to an OR, which results in a completely invalid truth table and a non-functioning circuit.
Why does my logic circuit output the exact opposite of what I calculated?
This usually happens during 'bubble pushing' on schematics. When you move an inversion bubble from the output of a gate to its inputs, you must change the gate type (AND becomes OR, OR becomes AND). If you simply move the bubbles and leave the gate shape the same, you have altered the logic function. Always verify your schematic changes by writing out the boolean equation and checking one row of the truth table with a multimeter or logic probe.
Does De Morgan's law apply to more than two variables?
Yes, the theorem scales infinitely. The complement of a 4-input AND gate NOT (A AND B AND C AND D) is exactly equivalent to (NOT A) OR (NOT B) OR (NOT C) OR (NOT D). In practice, this is how designers build wide-input NOR functions using standard 2-input NAND gates and an OR tree, avoiding the need for specialized, hard-to-source 4-input or 8-input logic ICs.
Mastering De Morgan's law for boolean algebra transitions you from simply reading schematics to actively optimizing them. By internalizing how inversion bars interact with AND and OR operators, you can troubleshoot inverted logic faults in PLC ladder diagrams, minimize propagation delays in high-speed digital buses, and reduce the physical footprint of your discrete logic designs.
