The Current Capacitor Formula: Derivation, Rearrangements, and Bench Examples

The fundamental current capacitor formula is i = C(dv/dt). In plain terms, the instantaneous current flowing through a capacitor equals its capacitance multiplied by the rate of change of the voltage across its terminals. If the voltage is steady (DC), the current is zero. If the voltage changes rapidly, the current spikes. This relationship is the bedrock of everything from power supply decoupling to analog filter design. Below, we will derive the formula, map out every algebraic rearrangement, and walk through solved problems with strict unit tracking to ensure your bench calculations match your oscilloscope readings.

The Core Current Capacitor Formula and Symbol Definitions

To understand where the formula comes from, we start with the basic definition of capacitance: the ability to store charge. The static equation is Q = C · V, where Q is charge in Coulombs, C is capacitance in Farads, and V is voltage. Current (i) is defined as the flow of charge over time (i = dQ/dt). If we take the derivative of the charge equation with respect to time, assuming capacitance C is constant, we get the definitive current capacitor formula:

i(t) = C · (dv(t) / dt)

Rearranged Forms: Solving for Any Variable

On the bench, you rarely need to solve for current directly. More often, you are sizing a capacitor to limit voltage droop, or calculating how long a charge cycle will take. Here are the algebraic rearrangements you will actually use:

• Solving for Capacitance (Sizing a decoupling cap): C = i / (dv/dt) or C = (i · dt) / dv
• Solving for Voltage Change (Calculating droop/ripple): dv = (i · dt) / C
• Solving for Time (Calculating charge/discharge duration): dt = (C · dv) / i
• Integral Form (Finding voltage from a known current waveform): v(t) = (1/C) ∫ i(t) dt + v(0)

When the Formula Applies (And When It Breaks)

The equation i = C(dv/dt) describes an ideal capacitor. In the real world, physical components have parasitic elements that break the math if you push them too hard.

The Ideal Assumptions

The formula assumes the capacitor has zero Equivalent Series Resistance (ESR), zero Equivalent Series Inductance (ESL), and infinite parallel insulation resistance. It also assumes the dielectric constant is perfectly linear (which is false for X7R/Y5V ceramics under DC bias, but true for C0G/NP0 and film capacitors).

Unit Mistakes That Break the Math

The number one reason hobbyists and junior engineers get answers off by a factor of a million is failing to convert bench units to base SI units.
The Trap: Plugging 100 μF directly into the equation as "100" instead of "0.0001" (or 100e-6).
The Fix: Always convert to Farads, Amperes, and Seconds before calculating, then convert the result back to engineering notation.

Realistic Answer Magnitudes

If your calculation yields 4,000 Amps for a small signal circuit, you haven't discovered a free energy source; you've ignored parasitic inductance. At extremely high dv/dt (like a 5V/ns logic edge), the ESL of the capacitor and the PCB traces will limit the actual peak current long before the ideal formula's prediction is reached. The formula tells you what the capacitor wants to draw; the parasitics dictate what it actually draws.

Worked Problem 1: DC Charging Transient

Scenario: You are designing a soft-start circuit. You need to charge a 470 μF electrolytic capacitor from 0V to 12V using a constant current source set to 50 mA. How long will the charging phase take?

Step 1: Identify knowns and convert to SI units.

• C = 470 μF = 470 × 10-6 F
• dv = 12V - 0V = 12 V
• i = 50 mA = 50 × 10-3 A

Step 2: Select the rearranged formula.

We need time, so we use: dt = (C · dv) / i

Step 3: Execute with unit tracking.

dt = (470 × 10-6 F · 12 V) / (50 × 10-3 A)
dt = (0.00564 C) / (0.05 A)
dt = 0.1128 seconds

Result: The capacitor will reach 12V in exactly 112.8 milliseconds. Because the current is constant, the voltage ramp is perfectly linear, which is exactly what you want for a predictable soft-start enable threshold.

Worked Problem 2: AC Ripple and Decoupling

Scenario: An ESP32-S3 microcontroller wakes from deep sleep and draws a transient current spike of 250 mA for 400 nanoseconds while the RF PHY initializes. You have a 100 nF (0.1 μF) MLCC placed right next to the VDD pin. Will the voltage droop (dv) exceed the brownout threshold of 150 mV?

Step 1: Identify knowns and convert to SI units.

• i = 250 mA = 0.25 A
• dt = 400 ns = 400 × 10-9 s
• C = 100 nF = 100 × 10-9 F

Step 2: Select the rearranged formula.

We need voltage change: dv = (i · dt) / C

Step 3: Execute with unit tracking.

dv = (0.25 A · 400 × 10-9 s) / (100 × 10-9 F)
dv = (100 × 10-9 C) / (100 × 10-9 F)
dv = 1.0 V

Result: The ideal droop is 1.0V (1000 mV), which massively exceeds the 150 mV brownout limit.
Practical Caveat: In reality, the bulk capacitor on the 3.3V rail and the PCB plane capacitance will supply some of this charge, and the ESL of the 100nF cap will limit the initial spike. However, relying on parasitics to save a poorly decoupled RF IC is a recipe for random reboots. Fix: Add a 10 μF bulk capacitor nearby to handle the lower-frequency energy demand, keeping the 100nF cap strictly for the sub-nanosecond edge transitions.

Real-World Scenario Walkthrough: The Blown MLCC on the 5V Rail

Formulas aren't just for passing exams; they explain why components explode on your bench. Here is a teardown of a real-world failure involving a misapplied snubber capacitor.

The Setup

A junior designer was building a 24V DC-DC buck converter. To tame high-frequency ringing on the switching (SW) node, they placed a 1 μF 0805 X7R MLCC directly from the SW node to ground, acting as a brute-force snubber. The MOSFET switched with a dv/dt of 40 V/ns during the dead-time transition.

The Numbers

Let's run the current capacitor formula to see what the component was asked to do.

• C = 1 μF = 1 × 10-6 F
• dv/dt = 40 V/ns = 40 × 109 V/s

i = C · (dv/dt)
i = (1 × 10-6 F) · (40 × 109 V/s)
i = 40,000 Amperes

The Outcome

Upon first power-up, the 0805 capacitor emitted a sharp crack, split open, and shorted internally, taking the high-side MOSFET down with it and pulling the 24V input rail to ground. The PCB trace leading to the capacitor pad was partially lifted from the FR4 substrate.

What Went Wrong

The designer looked at capacitance (1 μF) but ignored the dv/dt current magnitude. An 0805 MLCC has internal electrodes roughly the width of a human hair. Asking it to source or sink 40,000 Amps, even for a few nanoseconds, exceeds the physical current density limits of the metal layers, causing instantaneous vaporization. Furthermore, the massive inrush current interacted with the trace inductance, creating a destructive voltage ring.

The Correct Approach: Snubbers should use small capacitance values (typically 100 pF to 1 nF) made of C0G/NP0 dielectric, which handles high dv/dt gracefully. Better yet, use an RC snubber (a resistor in series with a smaller capacitor) to intentionally limit the peak current according to Ohm's law, rather than relying on the capacitor's parasitic ESR to do it accidentally.

Further Reading: For deeper insights into capacitor parasitics and high-frequency decoupling, refer to the Capacitors and Calculus chapter on All About Circuits, and review the AC Capacitance guide on Electronics Tutorials for phasor-domain applications.