Building Discrete Logic Gates with MOSFETs: A Practical CMOS Bench Guide

Why Build Discrete Logic Gates with MOSFETs?

If you need a simple AND or OR gate, you usually reach for a 74HC08 or 4081 IC. But building discrete logic gates with MOSFETs becomes necessary when you hit the edges of standard logic families. You do this when interfacing mismatched voltage domains (like translating 24V industrial PLC signals to 3.3V microcontroller GPIOs), when you need a gate to directly source or sink higher currents than a standard IC can handle, or when you are designing custom silicon layouts and need to understand the transistor-level switching that packaged ICs hide.

For bench work and prototyping, the safest default part numbers are the CD4007UB (a DIP-14 IC containing three discrete NMOS and three discrete PMOS transistors, typically around $0.80) or the discrete through-hole pair of 2N7000 (NMOS, 60V/200mA) and BS250 (PMOS, -45V/-230mA). These give you the raw building blocks of Complementary MOS (CMOS) logic without the constraints of fixed VCC limits found in pre-packaged logic gates.

The CMOS Inverter: Symbol, Pinout, and Operating Regions

The fundamental building block of MOSFET logic is the inverter (NOT gate). It uses one PMOS transistor for the pull-up network (connected to VDD) and one NMOS transistor for the pull-down network (connected to VSS/GND). The gates are tied together as the input, and the drains are tied together as the output.

Unlike analog amplifiers, logic MOSFETs are not biased in the saturation region. They are driven hard into the triode (linear) region to act as closed switches, or pushed into cutoff to act as open switches.

Biasing and Selecting MOSFETs for Logic Applications

Selecting a MOSFET for logic isn't about maximizing gain; it's about minimizing R_DS(on) (on-resistance) and managing gate capacitance. When biasing for logic, you want the gate voltage to swing rail-to-rail. A logic HIGH must be high enough to drive V_GS well above the threshold voltage (V_th), forcing the MOSFET deep into the triode region.

Selection Criteria:

• Threshold Voltage (V_gs(th)): For 5V logic, select MOSFETs with a V_th between 1.5V and 2.5V. If V_th is too high (e.g., 4V), a 5V logic HIGH won't fully turn on the device, leaving it in the high-resistance saturation region.
• Gate Capacitance (C_iss): Lower is better for high-speed logic. High C_iss slows down the switching edges, increasing the time both PMOS and NMOS are partially ON simultaneously (shoot-through current).
• Maximum V_GS: Most small-signal MOSFETs are rated for ±20V. Never exceed this, or the gate oxide will puncture.

Bench Walkthrough: Building a Discrete 2-Input NAND Gate

A NAND gate requires two PMOS transistors in parallel (pull-up) and two NMOS transistors in series (pull-down). If either input is LOW, at least one PMOS turns ON and one NMOS turns OFF, pulling the output HIGH. Both inputs must be HIGH to turn on the series NMOS path and pull the output LOW.

Component List:

• 2x BS250 (PMOS) or CD4007UB PMOS pairs
• 2x 2N7000 (NMOS) or CD4007UB NMOS pairs
• 2x 10kΩ resistors (Input pull-downs)
• 4x 100Ω resistors (Gate stoppers)
• 1x 10kΩ resistor (Output pull-down for defined state during high-impedance transitions)

1. Wire the Pull-Down Network: Connect the source of NMOS1 to Ground. Connect the drain of NMOS1 to the source of NMOS2. The drain of NMOS2 will be your output node.
2. Wire the Pull-Up Network: Connect the sources of both PMOS1 and PMOS2 to VDD (e.g., 5V or 12V). Tie their drains together and connect them to the output node (the drain of NMOS2).
3. Add Gate Stoppers: Solder a 100Ω resistor in series with each of the four gate pins. This dampens high-frequency parasitic ringing caused by breadboard trace inductance and gate capacitance.
4. Establish Inputs: Tie the gates of NMOS1 and PMOS1 together to form Input A. Tie NMOS2 and PMOS2 gates together for Input B. Connect a 10kΩ resistor from each input to Ground to prevent floating gates when switches are open.
5. Verify: Power the circuit. Measure the output with a multimeter. With both inputs grounded (LOW), output should read VDD. Ground Input A and apply VDD to Input B; output should remain VDD. Apply VDD to both inputs; output should drop to <0.2V.

When It Goes Wrong: A Real-World Failure Scenario

Abstract theory rarely warns you about voltage domain mismatches. Here is a scenario from the bench that resulted in a melted breadboard jumper.

The Setup: I needed to drive a 12V automotive relay using a logic signal from a 3.3V ESP32. Instead of using a dedicated logic-level translator, I built a discrete CMOS inverter using a BS250 (PMOS) and 2N7000 (NMOS) powered by a 12V supply. The ESP32 GPIO was wired directly to the gates of both MOSFETs.

The Numbers: VDD = 12V. ESP32 Logic HIGH = 3.3V. ESP32 Logic LOW = 0V.

The Outcome: When the ESP32 pin went HIGH (3.3V), the output node hovered around 6V, the 2N7000 became too hot to touch within three seconds, and the ESP32 browned out and reset.

What Went Wrong (Shoot-Through): I forgot to calculate V_GS relative to the source, not ground. For the NMOS (source at 0V), a 3.3V gate yields V_GS = 3.3V. Since the 2N7000 V_th is typically 2.1V, it turned ON. For the PMOS (source at 12V), a 3.3V gate yields V_GS = 3.3V - 12V = -8.7V. The BS250 requires a V_GS of roughly -2.5V to turn on. Because -8.7V is well beyond the threshold, the PMOS also turned ON hard. Both transistors were fully saturated in the triode region simultaneously, creating a near-dead short from 12V to Ground. The only thing limiting the current was the R_DS(on) of the MOSFETs and the breadboard traces. Always use a proper level shifter or a dedicated gate driver when crossing voltage domains.

Testing and Troubleshooting MOSFET Logic with a Multimeter

MOSFETs in logic circuits typically fail in two ways: gate oxide puncture from ESD or overvoltage (resulting in a permanent short from gate to channel), or thermal destruction from shoot-through (resulting in a short from drain to source).

Here is how to test a discrete logic MOSFET on the bench using a standard digital multimeter (DMM):

1. Test for Gate Leakage (Oxide Integrity): Set your DMM to the highest resistance range (usually 20MΩ or 200MΩ). Measure between the Gate and Source, and Gate and Drain. A healthy MOSFET will read 'OL' (Over Limit) or infinite resistance. If you read anything less than 10MΩ, the gate oxide is compromised. Throw it in the bin.
2. Test the Body Diode: Set the DMM to Diode Test mode. For an NMOS, place the red probe on the Source and the black probe on the Drain. You should read a forward voltage drop of roughly 0.5V to 0.7V. Reverse the probes; it should read 'OL'. If it reads near 0.0V in both directions, the drain-source channel has melted shorted.
3. Test Switching Action: While in Diode Test mode (red on Source, black on Drain for NMOS), use a jumper wire to briefly touch the Gate to the Drain (or a positive supply). The MOSFET should turn on, and the DMM should drop to near 0.0V. Short the Gate to the Source to discharge the gate capacitance; the DMM should return to reading the 0.5V body diode drop.

Building discrete logic gates with MOSFETs bridges the gap between digital abstraction and analog reality. By respecting threshold voltages, managing gate capacitance, and strictly controlling voltage domains, you can build robust, custom logic interfaces that off-the-shelf 74-series chips simply cannot handle.

References:
Texas Instruments CD4007UB CMOS Dual Complementary Pair Product Page
All About Circuits: CMOS Gate Circuitry