A capacitor voltage divider scales AC signals using series capacitance rather than resistance. The output voltage ($V_{out}$) taken across the lower capacitor ($C_2$) is calculated as $V_{out} = V_{in} \times \frac{C_1}{C_1 + C_2}$. Unlike a resistive divider where the larger resistor drops more voltage, in a capacitive divider, the smaller capacitor drops the larger share of the voltage because capacitive reactance ($X_c$) is inversely proportional to capacitance.
This topology is essential for high-frequency signal attenuation, RF probing, and AC coupling where zero real power dissipation is required. Below, we break down the node behavior, contrast it with resistive alternatives, and walk through a bench-tested 10:1 attenuator design using real component values.
Topology and Node Behavior (The Inverse Rule)
The standard topology consists of an AC voltage source ($V_{in}$), a series capacitor ($C_1$), a shunt capacitor ($C_2$) tied to ground, and an output node ($V_{mid}$) at their junction. The impedance of each capacitor is $Z = \frac{1}{j\omega C}$. When you apply the standard voltage divider formula $V_{mid} = V_{in} \times \frac{Z_2}{Z_1 + Z_2}$, the frequency and imaginary terms cancel out, leaving the purely capacitive ratio.
Because hobbyists and technicians frequently confuse the voltage drop direction, the table below maps exactly how the circuit behaves when component values shift or when hard faults occur.
| Component Change / Fault | Effect on $V_{mid}$ (Amplitude) | Effect on Phase / Impedance | Real-World Consequence |
|---|---|---|---|
| $C_1$ Increases | $V_{mid}$ Increases | Total series impedance drops | Attenuation ratio decreases; more signal passes to the load. |
| $C_2$ Increases | $V_{mid}$ Decreases | Shunt impedance drops | Attenuation ratio increases; signal is shunted to ground more aggressively. |
| $C_1$ Fails Short | $V_{mid} = V_{in}$ (0% attenuation) | Impedance approaches zero | Catastrophic: Full input voltage hits downstream ICs, likely destroying ADCs or op-amps. |
| $C_1$ Fails Open | $V_{mid} = 0V$ (AC) | Infinite series impedance | Signal path broken. Node floats to DC bias (if bleeder resistor is present). |
| $C_2$ Fails Short | $V_{mid} = 0V$ | Shunt impedance is zero | Signal is dead-shorted to ground. Upstream driver may overcurrent if not protected. |
| $C_2$ Fails Open | $V_{mid} = V_{in}$ (Undefined DC) | Shunt path removed | AC signal passes, but DC operating point floats wildly, causing ADC clipping or saturation. |
While capacitors are sometimes used to drop 120V/230V AC mains for low-power LED drivers (capacitive droppers), never use this topology for hobbyist mains interfacing. It provides zero galvanic isolation from the grid. A single fault or accidental touch of the "grounded" side can be lethal. Always use an isolated transformer or a certified Hi-Link HLK-PM01 style AC-DC module for mains-to-DC conversion on the bench.
Capacitive vs. Resistive Dividers: When to Use Which
Why choose a capacitor voltage divider over a standard resistive one? The decision hinges on power dissipation, frequency response, and DC isolation. Resistive dividers are broadband and handle DC, but they burn power as heat. Capacitive dividers are reactive—they store and release energy, resulting in theoretically zero real power loss (watts), though they do draw reactive current (VARs).
| Criterion | Resistive Divider | Capacitive Divider |
|---|---|---|
| DC Response | Passes DC and AC equally | Blocks DC entirely (AC only) |
| Power Dissipation | High ($I^2R$ losses generate heat) | Near Zero (Reactive power only) |
| Frequency Dependence | None (until parasitic capacitance takes over at VHF) | Highly dependent (requires minimum AC frequency to function) |
| Phase Shift | 0° (Voltage and current in phase) | Current leads voltage by 90° in the series branch |
| Best Application | DC biasing, low-frequency sensor scaling | RF attenuation, AC coupling, high-voltage AC probing |
Choose the capacitive topology when you need to attenuate an AC signal without loading the source with a resistive current draw, or when you need to inherently block a DC offset. Choose the resistive topology when your signal contains critical DC information or when operating at very low frequencies (e.g., 1Hz) where the required capacitor values would become physically massive and expensive.
Design Walkthrough: Building a 10:1 AC Signal Attenuator
Let’s design a divider to attenuate a 50V peak-to-peak, 100kHz RF signal down to roughly 4.5Vpp to safely feed a 5V microcontroller ADC. We need an attenuation ratio of approximately 1/11.
Using the formula $Ratio = \frac{C_1}{C_1 + C_2}$, if we set $C_1 = 1nF$, we need $C_2 = 10nF$ to achieve $\frac{1}{1 + 10} = \frac{1}{11}$ (0.0909).
Component Selection: Dielectric type is critical here. Standard X7R or Y5V ceramics exhibit severe voltage coefficient (capacitance drops as voltage rises) and microphonics. For signal integrity, you must use C0G/NP0 dielectrics, which are linear and stable. According to KEMET's dielectric guidelines, C0G maintains its value regardless of applied AC voltage or temperature shifts.
- $C_1$: 1nF, 100V, C0G (KEMET Part: C315C102J1G5TA) — ~$0.25
- $C_2$: 10nF, 100V, C0G (KEMET Part: C315C103J1G5TA) — ~$0.35
- $R_{bleed}$: 1MΩ, 1/4W Carbon Film — ~$0.02
The Bleeder Resistor: A capacitor voltage divider has an undefined DC operating point. If static charge builds up on $V_{mid}$, it will float outside the ADC's common-mode range. Placing a 1MΩ resistor in parallel with $C_2$ provides a DC path to ground. At 100kHz, the impedance of $C_2$ (10nF) is roughly 159Ω. The 1MΩ resistor is nearly 6,000 times larger, meaning it will not measurably affect the AC attenuation ratio, but it firmly anchors the DC bias at 0V.
Breadboard Testing and Verification Steps
Testing high-frequency reactive circuits on a solderless breadboard introduces parasitic capacitance (typically 2pF to 5pF per contact strip). While negligible at 1kHz, at 100kHz and above, you must keep leads short. Follow this verification sequence:
- De-energize and Verify: Ensure your signal generator is off. Use a multimeter to verify the breadboard ground rail is continuous and reads 0Ω to your bench ground.
- Place Components: Insert $C_1$ and $C_2$ in series. The junction between them is your $V_{mid}$ node. Keep the physical distance between the capacitor leads under 5mm to minimize parasitic trace inductance.
- Install Bleeder: Place the 1MΩ resistor directly across $C_2$ (from $V_{mid}$ to GND).
- Inject Signal: Connect your function generator (e.g., Siglent SDG1032X) to $V_{in}$. Set it to 100kHz, Sine wave, 50Vpp (ensure your generator's amplifier can swing this; if not, use 10Vpp and scale your expectations).
- Measure: Connect an oscilloscope probe (set to 10X attenuation) to $V_{mid}$. You should read exactly $\frac{1}{11}$ of the input amplitude. If you injected 10Vpp, $V_{mid}$ should read ~0.91Vpp.
- Check DC Offset: Switch the scope to DC coupling. The waveform should be centered exactly on 0V. If it is offset, your bleeder resistor is open or the wrong value.
If your measured $V_{mid}$ is consistently lower than the math predicts at high frequencies, breadboard parasitic capacitance ($C_{stray}$) is adding itself in parallel with $C_2$. If $C_2$ is 10nF and $C_{stray}$ is 5pF, the error is negligible. But if you scale this circuit down to $C_1 = 1pF$ and $C_2 = 10pF$ for GHz work, that 5pF breadboard stray will destroy your ratio. For ultra-high impedance dividers, you must build the circuit "dead-bug" style in free air or on a custom PCB with a ground plane.
What Breaks at the Extremes?
Understanding the failure modes of a capacitor voltage divider is critical when designing protection circuits for sensitive downstream electronics. Unlike resistors, which typically fail open when subjected to overvoltage, ceramic capacitors tend to fail short due to dielectric puncture.
If $C_1$ experiences a voltage spike exceeding its 100V rating and fails short, the full $V_{in}$ is instantly applied to $V_{mid}$. If this divider is feeding a 3.3V microcontroller ADC, the silicon will be destroyed in microseconds. To prevent this, professional designs often place a clamp diode (like a BAT54S Schottky) or a transient voltage suppression (TVS) diode at $V_{mid}$ to shunt overvoltage to the rails.
Conversely, if $C_2$ fails short, the signal is grounded. While this protects the ADC, it creates a dead short across the AC source. If your signal generator lacks short-circuit protection, its output stage could overheat. Always design your $C_1$ value such that its maximum reactive current ($I = \frac{V_{in}}{X_{c1}}$) remains within the safe drive limits of your upstream source. For a 1nF capacitor at 100kHz and 50V, the current is roughly 31mA—well within the limits of most bench equipment, but something to watch if scaling up to mains frequencies and larger capacitances.
For deeper insights into driving ADCs with passive networks and managing the charge-kickback effects that can interact with capacitive dividers, refer to Texas Instruments' application notes on SAR ADC input conditioning. The interplay between your divider's output impedance and the ADC's internal sampling capacitor is often the hidden culprit behind noisy or inaccurate readings.
