To calculate the resonant frequency of an LC circuit, use the formula fr = 1 / (2π√LC). At this specific frequency, the inductive reactance (XL) and capacitive reactance (XC) are equal in magnitude but opposite in phase, effectively canceling each other out. For example, pairing a 25 µH inductor with a 1 nF capacitor yields a resonant frequency of exactly 1.006 MHz. At resonance, the circuit's impedance drops to near zero (limited only by the parasitic resistance of the wire and component leads), allowing maximum current to flow.
While the math is straightforward, translating this formula into a physical, functioning circuit requires navigating component parasitics, topology selection, and failure modes. This guide breaks down the physical design of a series LC bandpass filter, contrasting it with parallel alternatives, and provides a step-by-step breadboard verification process.
Series vs. Parallel Topology: Why Choose Series?
An LC circuit can be wired in two fundamental configurations: series or parallel. The choice dictates whether the circuit acts as a bandpass filter (passing the resonant frequency) or a bandstop/tank circuit (blocking or storing the resonant frequency).
- Series LC Topology: The inductor and capacitor are wired end-to-end in the signal path (Node IN → L → Node MID → C → Node OUT). At resonance, impedance is at its minimum. This topology is ideal for inline RF bandpass filtering, impedance matching networks, and passing a specific carrier frequency while blocking DC and out-of-band noise.
- Parallel LC Topology (Tank Circuit): The inductor and capacitor are wired in parallel with each other, typically between the signal line and ground. At resonance, impedance is at its maximum. This is preferred for oscillator tanks, notch filters, and IF (Intermediate Frequency) traps where you need to block a specific frequency or sustain oscillation.
Why choose the series topology for this design? When designing a signal routing filter (e.g., extracting a 1 MHz carrier from a mixed-signal environment), a series LC acts as a highly selective gate. A parallel LC would require a shunt configuration that dumps the target frequency to ground, which is less efficient for inline signal extraction and can load down the preceding driver stage if not buffered properly.
Element Sensitivity and Failure Mode Matrix
Understanding how component drift or catastrophic failure affects the circuit is critical for debugging. The table below maps the behavioral shifts and hard failure modes for both topologies. Note how an open or short fault yields drastically different results depending on the wiring configuration.
| Component Fault / Change | Effect on fr | Series LC Result (Bandpass) | Parallel LC Result (Notch/Tank) |
|---|---|---|---|
| Increase L or C value | Decreases | Passband shifts lower; insertion loss may increase | Notch frequency shifts lower; Q-factor drops |
| Decrease L or C value | Increases | Passband shifts higher; bandwidth widens | Notch frequency shifts higher |
| Short Inductor (L) | N/A | Circuit becomes high-pass (capacitor blocks DC, passes HF) | Signal shorted to GND (kills all frequencies) |
| Open Inductor (L) | N/A | Signal path broken (zero output at all frequencies) | Circuit becomes high-pass (capacitor passes HF to GND) |
| Short Capacitor (C) | N/A | Passes all HF (inductor only); blocks DC | Signal shorted to GND (kills all frequencies) |
| Open Capacitor (C) | N/A | Signal path broken (zero output at all frequencies) | Circuit becomes low-pass (inductor passes LF to GND) |
Note: In a series topology, any "open" fault breaks the primary signal path entirely, resulting in a dead circuit. In a parallel topology, an "open" fault simply removes one leg of the tank, degrading it to a single-component shunt filter rather than killing the main signal path.
Design Walkthrough: 1 MHz Series LC Bandpass Filter
Let’s design a series LC bandpass filter tuned to 1.0 MHz. We will use the rearranged resonant formula to find our required LC product:
LC = 1 / (2πfr)²
LC = 1 / (2π × 1,000,000)² = 2.533 × 10-11 seconds².
1. Selecting the Capacitor (C)
We need to pick a standard capacitor value first, as capacitor tolerances and dielectric behaviors are generally more restrictive than inductors. Let’s choose C = 1 nF (1000 pF).
2. Calculating the Inductor (L)
With C fixed at 1 × 10-9 F, we solve for L:
L = (2.533 × 10-11) / (1 × 10-9) = 25.33 µH.
We will select a standard 25 µH RF choke. However, we must check the inductor's Self-Resonant Frequency (SRF). Every physical inductor has parasitic parallel capacitance between its windings. If the SRF is close to our 1 MHz target, the inductor stops acting like an inductor. The Coilcraft 1812PS-253 (25 µH) has an SRF of roughly 11 MHz, providing a safe margin for a 1 MHz design.
3. Node Mapping and Topology
- Node 1 (IN): Signal source (e.g., Function Generator 50Ω output).
- Node 2 (Junction): Connection between L1 anode and C1 anode.
- Node 3 (OUT): C1 cathode, connected to the load resistor (e.g., 1 kΩ to GND) and oscilloscope probe.
For a deeper theoretical breakdown of the impedance vectors at play in this configuration, refer to the Series LCR Circuit guide on Electronics Tutorials.
Breadboard Verification and Parasitic Mitigation
Testing high-frequency LC circuits on a solderless breadboard introduces parasitic elements that can skew your measurements. Follow this step-by-step procedure to verify your 1 MHz design accurately.
Step 1: Account for Breadboard Stray Capacitance
A standard solderless breadboard introduces approximately 2 pF to 5 pF of stray capacitance between adjacent metal clips. In a 1 MHz circuit with a 1 nF capacitor, an extra 3 pF of stray capacitance will shift your resonant frequency down by roughly 1.5 kHz. This is acceptable for bench verification, but if you were designing for 50 MHz, breadboard parasitics would render the circuit unusable. Keep L and C leads as short as possible and avoid spanning them across the breadboard's center trench if unnecessary.
Step 2: Probe Grounding Technique
Do not use the standard 6-inch alligator ground clip on your oscilloscope probe. At 1 MHz, that loop of wire acts as an antenna and introduces roughly 15 nH of parasitic inductance, which will cause high-frequency ringing on your rising edges. Instead, remove the plastic probe tip cover and use the spring-ground attachment to connect directly to the circuit's local ground node. This minimizes the ground loop area and ensures a clean Bode plot trace.
Step 3: Frequency Sweep and -3dB Measurement
- Set your function generator to output a 1 Vpp sine wave with 0 V DC offset.
- Sweep the frequency logarithmically from 100 kHz up to 5 MHz.
- Monitor Node 3 (OUT) on your oscilloscope. You should see the voltage amplitude peak sharply around 1.006 MHz.
- Identify the peak voltage (Vmax). Calculate the -3dB threshold (Vmax × 0.707).
- Find the lower frequency (fL) and upper frequency (fH) where the voltage drops to this -3dB threshold.
- Calculate the Bandwidth (BW = fH - fL) and the Q-factor (Q = fr / BW). A high Q (narrow peak) indicates low parasitic resistance in your Coilcraft inductor.
Step 4: Verify DC Blocking
Because the capacitor is in the primary signal path, the series LC topology inherently blocks DC. Switch your function generator to a 1 kHz square wave with a 500 mV DC offset. The oscilloscope should show the AC square wave passing through (albeit heavily attenuated and phase-shifted, as 1 kHz is far below the 1 MHz passband), but the 500 mV DC offset must be completely absent at Node 3. If DC is present, your capacitor is either shorted or you have a breadboard short bypassing the component.
For further reading on managing parasitics and Q-factor degradation in physical LC implementations, Analog Devices provides excellent practical insights in their Ask The Applications Engineer archives.
