Why Build Logic Gates with Transistors on the Bench?

If you just need a NAND gate, a 74HC00 IC costs about $0.15 and saves you an hour of wiring. So why bother building logic gates with transistors? Because off-the-shelf logic ICs lock you into 5V or 3.3V rails and max out at ~25mA of drive current. When you need to interface a 24V industrial PLC signal with a 3.3V microcontroller, or switch a 100mA relay coil directly from a logic state without an intermediate driver IC, discrete transistor logic is the most robust tool in your kit.

Building these gates from scratch forces you to confront the physical realities of semiconductor junctions, threshold voltages, and floating nodes. This guide strips away the abstract textbook physics and focuses entirely on what happens on the breadboard when you wire up discrete silicon.

Safe Default Part Numbers: For BJT logic, use the 2N3904 (NPN, 40V Vce, 200mA Ic, ~$0.04/ea). For MOSFET logic, use the 2N7000 (N-Channel, 60V Vds, 200mA Id, ~$0.06/ea). Both come in through-hole TO-92 packages and are universally available.

Pinouts and the Terminology Trap

Before wiring, you must understand the physical pinout and the terminology differences between BJTs and MOSFETs. Both the 2N3904 and 2N7000 use the TO-92 package. Hold the component with the flat side facing you and the legs pointing down:

  • 2N3904 (NPN BJT): Pin 1 = Emitter (E), Pin 2 = Base (B), Pin 3 = Collector (C).
  • 2N7000 (N-MOSFET): Pin 1 = Source (S), Pin 2 = Gate (G), Pin 3 = Drain (D).

MOSFET Operating Regions for Logic

Textbooks often confuse hobbyists by using the word "saturation" differently for BJTs and MOSFETs. In a BJT, saturation means the switch is fully ON. In a MOSFET, the "saturation" region actually means the device is acting as a constant current source (partially ON). For digital logic, we want the MOSFET in the Triode (or Linear) region to act as a closed switch. Refer to the table below for typical biasing targets.

Operating Region Gate-Source Voltage (Vgs) Drain-Source State Role in Digital Logic
Cutoff < 2.0V (Below Vgs_th) Open Circuit (Id ≈ 0) Logic HIGH output (via pull-up)
Triode / Linear > 4.5V (Fully Enhanced) Closed Switch (Rds_on ≈ 5Ω) Logic LOW output (pulling to GND)
Saturation (Active) 2.5V - 4.0V (Partial) Current Source (High Vds drop) Avoid: Causes logic ambiguity & heat

Complete Application Circuit: 2-Input NMOS NAND Gate

The easiest discrete logic gate to build with modern components is a NAND gate using N-channel MOSFETs. Unlike BJT RTL (Resistor-Transistor Logic) which requires careful base-current biasing, NMOS logic is voltage-controlled, drawing virtually zero steady-state current from the input source.

Component List & Values

  • Q1, Q2: 2N7000 N-Channel MOSFETs
  • R1 (Pull-up): 1kΩ resistor (Limits current to 5mA when output is LOW)
  • R2, R3 (Gate Pull-downs): 10kΩ resistors (Prevents floating gates from turning on via stray EMI)
  • Power Supply: 5.0V DC

Wiring the NAND Gate

  1. Connect the Source of Q1 directly to Ground (GND).
  2. Connect the Drain of Q1 to the Source of Q2. This series stack is the core of the NAND logic.
  3. Connect the Drain of Q2 to one end of the 1kΩ pull-up resistor (R1). Connect the other end of R1 to the 5V rail.
  4. The Output node is the junction between Q2's Drain and R1.
  5. Wire Input A to the Gate of Q1. Wire a 10kΩ resistor from Gate Q1 to GND.
  6. Wire Input B to the Gate of Q2. Wire a 10kΩ resistor from Gate Q2 to GND.

Logic Verification: If either Input A or Input B is LOW (0V), its respective MOSFET turns off, breaking the path to ground. The 1kΩ pull-up pulls the Output to 5V (Logic HIGH). Only when both inputs are HIGH do both MOSFETs turn on, pulling the Output down to GND (Logic LOW). For a deep dive into the underlying semiconductor physics of these junctions, the All About Circuits semiconductor textbook provides excellent foundational theory.

Bench Scenario: The 3.3V Microcontroller Trap

Theory is clean; the bench is messy. Here is a real-world scenario that traps almost every maker transitioning from 5V Arduinos to 3.3V ESP32 boards.

The Setup

I was building a custom interlock circuit for a 3D printer using an ESP32-S3 (which outputs 3.3V logic). I wired the NMOS NAND gate exactly as described above, powering the pull-up resistor with 5V to interface with a 5V stepper driver enable pin. I drove Input A and Input B directly from the ESP32 GPIO pins.

The Numbers and The Outcome

When both inputs were LOW, the output correctly read 4.98V. But when I set both GPIO pins HIGH (3.3V), the output only dropped to 1.8V instead of the expected <0.2V. The 5V stepper driver interpreted 1.8V as an undefined state and occasionally faulted.

What Went Wrong?

Look at the datasheet for the 2N7000 MOSFET. The Gate-Source Threshold Voltage (Vgs_th) is specified between 2.0V and 3.0V. At 3.3V, the ESP32 is barely providing enough voltage to turn the MOSFET on. Worse, look at Q2 (the top transistor). Its Source is not connected to GND; it is connected to the Drain of Q1. When Q1 turns on, it drops about 0.1V. That means the Source of Q2 sits at 0.1V. If the Gate of Q2 is driven to 3.3V, the actual Vgs of Q2 is 3.3V - 0.1V = 3.2V. Furthermore, as current flows and Q2 heats up, its threshold voltage shifts. Q2 was stuck in the high-resistance Triode/Saturation boundary, acting like a 400Ω resistor instead of a 5Ω switch. The 1kΩ pull-up and the 400Ω MOSFET formed a voltage divider, resulting in the 1.8V output.

The Fix

You cannot reliably drive a 5V NMOS logic gate directly from a 3.3V microcontroller without a gate driver. I replaced the direct GPIO connection with a cheap BSS138 logic-level translator, boosting the 3.3V gate signals to 5V. The output immediately dropped to a crisp 0.05V.

Failure Modes and Multimeter Diagnostics

Discrete transistors fail in predictable ways, usually due to electrostatic discharge (ESD) blowing the gate oxide, or thermal runaway from exceeding current ratings. Here is how to test a 2N7000 MOSFET on the bench using a standard digital multimeter (DMM) set to Diode Test mode.

Step-by-Step MOSFET Testing

  1. Discharge the Gate: Touch the Gate and Source pins together with your finger or a piece of wire. This bleeds off any stray static charge that might be partially turning the device on.
  2. Test the Body Diode: Place the Red probe on the Drain (Pin 3) and the Black probe on the Source (Pin 1). You should read a forward voltage drop of roughly 0.5V to 0.6V. This is the internal parasitic body diode.
  3. Test Reverse Block: Swap the probes (Red on Source, Black on Drain). The meter should read OL (Over Limit), indicating the diode is blocking reverse current.
  4. Check for Gate Oxide Rupture: Place one probe on the Gate (Pin 2) and the other on the Source (Pin 1). It must read OL. If you read a dead short or a low resistance (e.g., 40Ω), the microscopic silicon dioxide layer inside the gate has been punctured by ESD. Throw it in the bin.
Bench Safety Note: Never leave the Gate pin of a MOSFET floating while the circuit is powered. A floating gate acts as an antenna, picking up 50/60Hz mains hum and rapidly switching the transistor in and out of the linear region. This causes massive heat dissipation and will literally melt the TO-92 plastic casing in seconds. Always use 10kΩ pull-down resistors on every gate input.

Building logic gates with transistors bridges the gap between writing code and understanding the silicon that executes it. Whether you are designing a custom high-voltage interlock or just trying to understand why your 3.3V logic isn't switching a 5V load, mastering discrete RTL and NMOS logic gives you total control over the physical layer of your electronics projects.