To build reliable transistor logic circuits, you must operate Bipolar Junction Transistors (BJTs) or Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) strictly as switches—driving them between their cutoff (OFF) and saturation/ohmic (ON) regions. For 5V hobbyist and prototype logic, the 2N3904 (NPN BJT, 40V/200mA) and the 2N7000 (N-Channel MOSFET, 60V/200mA) are the safest, most widely available default part numbers. By combining these discrete components with pull-up and current-limiting resistors, you can replicate any Boolean logic gate without relying on integrated circuits.
The Core Building Blocks: BJT vs. MOSFET Logic
When designing discrete logic gates, your choice between a BJT and a MOSFET dictates your biasing network, input impedance, and power consumption. Both devices feature three terminals, but their control mechanisms differ fundamentally.
Pinout and Symbol Descriptions
- BJT (NPN): The Base is the control terminal (current-driven). The Collector connects to the load or pull-up resistor (output). The Emitter connects to the ground reference. In circuit symbols, the emitter arrow points outward, indicating conventional current flow out of the device.
- MOSFET (N-Channel): The Gate is the control terminal (voltage-driven, virtually zero static current). The Drain connects to the load or pull-up resistor. The Source connects to ground. The symbol features a distinct gap between the gate and the channel, representing the silicon dioxide insulating layer.
Operation Regions and Biasing for Digital Switching
In analog amplifiers, transistors operate in the active/linear region. In transistor logic circuits, that region is a failure state. You must bias the device to snap between the extremes. For a BJT, this means supplying enough base current ($I_B$) to force the collector-emitter voltage ($V_{CE}$) below 0.2V. For a MOSFET, it means applying a gate-source voltage ($V_{GS}$) well above the threshold voltage ($V_{th}$) to minimize the drain-source resistance ($R_{DS(on)}$).
| Region | BJT State (NPN) | MOSFET State (N-Ch) | Typical V_CE / V_DS | Logic Equivalent |
|---|---|---|---|---|
| Cutoff | OFF (V_BE < 0.6V) | OFF (V_GS < V_th) | ~5.0V (Pulled High) | Logic HIGH (1) |
| Active / Saturation | Amplifying (Avoid) | Constant Current (Avoid) | 0.5V to 4.5V | Undefined / Invalid |
| Hard Saturation / Ohmic | ON (I_B > I_C / β) | ON (V_GS > 4.5V) | < 0.2V (BJT) / < 0.1V (FET) | Logic LOW (0) |
To select the right biasing resistor for a BJT, use the forced-beta rule. If your collector load draws 1mA, and your transistor has a minimum DC current gain ($h_{FE}$) of 100, you need at least 10µA of base current. In practice, overdrive the base by a factor of 2 to 5 to guarantee hard saturation. For a 5V logic input driving a 2N3904 through a 10kΩ base resistor, $I_B = (5V - 0.7V) / 10kΩ = 0.43mA$, which easily saturates a 1mA collector load.
Complete Application Circuit: 2-Input Discrete NAND Gate
The NAND gate is universal; any Boolean function can be built from it. Below is a complete, breadboard-ready schematic for a 2-input NAND gate using discrete NPN BJTs. This topology mimics the input stage of classic 7400-series TTL logic.
Component List
- Q1, Q2: 2N3904 NPN Transistors
- R_Pullup: 4.7kΩ resistor (1/4W)
- R_B1, R_B2: 10kΩ resistors (1/4W)
- Power Supply: 5.0V DC
Wiring Steps
- Establish the Pull-Up: Connect one end of the 4.7kΩ R_Pullup to the 5V VCC rail. Connect the other end to the Collector of Q1. This node is also your Logic Output.
- Stack the Transistors: Connect the Emitter of Q1 directly to the Collector of Q2. This series arrangement ensures current can only flow to ground if both transistors are turned ON.
- Ground the Return: Connect the Emitter of Q2 to the system Ground (GND).
- Wire Input A: Connect Input A to the Base of Q1 through the 10kΩ R_B1 resistor.
- Wire Input B: Connect Input B to the Base of Q2 through the 10kΩ R_B2 resistor.
Failure Modes and Multimeter Diagnostics
Discrete transistors in logic circuits rarely fail from normal switching. They fail from thermal runaway, overvoltage transients, or electrostatic discharge (ESD). BJTs typically fail shorted (Collector-to-Emitter), while MOSFETs usually fail with a punctured gate oxide, resulting in a short between the Gate and Source.
How to Test a BJT with a Digital Multimeter
You do not need a specialized transistor tester. Set your multimeter to Diode Test mode and follow this decision path for an NPN transistor like the 2N3904:
- Base-Emitter Junction: Place the Red probe on the Base and Black on the Emitter. You should read a forward voltage drop between 0.60V and 0.75V. Reverse the probes; the meter must read OL (Open Loop).
- Base-Collector Junction: Place Red on Base, Black on Collector. Expect 0.60V to 0.75V. Reverse probes; expect OL.
- Collector-Emitter Path: Probe between Collector and Emitter in both directions. Both must read OL. If you read a short (near 0.00V) or a low resistance, the transistor is destroyed and must be replaced.
Reference: For exact pinout orientations and maximum thermal limits, always verify against the manufacturer datasheet, such as the ON Semiconductor 2N3904 Datasheet.
Frequently Asked Questions About Transistor Logic Circuits
Why do discrete transistor logic circuits consume more power than CMOS ICs?
Discrete BJT logic circuits, like the NAND gate detailed above, draw continuous current through the pull-up resistor and the base-emitter junctions whenever the output is pulled LOW. This static power dissipation generates heat and drains batteries quickly. In contrast, Complementary MOS (CMOS) integrated circuits use paired P-channel and N-channel MOSFETs. Because MOSFET gates are voltage-controlled and draw virtually zero steady-state current, a CMOS IC only consumes significant power during the microsecond it takes to switch states.
Can I mix NPN and PNP transistors in the same logic gate?
Yes, and doing so is highly recommended for output stages. Mixing NPN and PNP BJTs allows you to build a "Totem-Pole" output, which actively drives the output HIGH (via the PNP or upper NPN) and actively drives it LOW (via the lower NPN), eliminating the need for a passive pull-up resistor. This drastically reduces propagation delay and improves noise immunity. In MOSFET logic, pairing an N-Channel and P-Channel FET creates a discrete CMOS inverter, which is the foundational building block of modern microprocessors.
How do I prevent floating inputs in discrete MOSFET logic?
A floating MOSFET gate is a high-impedance antenna. Stray electromagnetic interference can induce a voltage on the gate that partially turns the transistor on, placing it in the high-resistance linear region where it will rapidly overheat and destroy itself. To prevent this, always tie unused or potentially disconnected inputs to a defined logic state. Use a 100kΩ pull-down resistor to ground for N-Channel MOSFETs, or a 100kΩ pull-up resistor to VCC for P-Channel MOSFETs, ensuring the gate defaults to a safe OFF state when the driving signal is removed.
What is the propagation delay of a discrete transistor logic gate?
Discrete transistor logic is significantly slower than integrated logic families like 74HC or 4000-series CMOS. The delay is primarily caused by the Miller effect (parasitic capacitance between the collector/base or drain/gate) and the time required to inject and remove charge carriers from the BJT base region. A discrete BJT NAND gate typically exhibits a propagation delay of 50ns to 150ns, whereas a discrete MOSFET gate might switch in 20ns to 50ns. For high-speed digital buses or clock generation, discrete logic is unsuitable, and you should rely on dedicated logic ICs. For further reading on switching speeds and capacitance, see All About Circuits: Transistor Switching.
