When you are reading a digital logic schematic or tracing a PCB layout, boolean symbols act as the visual shorthand for binary operations. However, the exact shape drawn on the page depends entirely on the drafting standard the engineer used. In the US and in academic settings, you will predominantly see the distinctive curved shapes defined by ANSI/IEEE. In European industrial environments, PLC programming, and modern international datasheets, the rectangular outlines of the IEC standard dominate. Misinterpreting these symbols—especially when dealing with faded legacy blueprints—can lead to incorrect wiring, blown ICs, or hours of wasted debugging time.
The Complete Boolean Logic Symbol Reference
The table below maps the seven fundamental logic gates across both major standards. We have also included the typical propagation delay for standard 74HC-series CMOS ICs (measured at 5V, 25°C) to give you a bench-level expectation of timing when swapping between gate types.
| Gate Name | Boolean Expression | ANSI/IEEE 91 Shape | IEC 60617-12 Symbol | Typical 74HC Delay |
|---|---|---|---|---|
| AND | Q = A · B | D-shape (flat back, curved front) | Rectangle with '&' or '1' inside | ~14 ns (74HC08) |
| OR | Q = A + B | Curved back, pointed front (shield) | Rectangle with '≥1' inside | ~14 ns (74HC32) |
| NOT (Inverter) | Q = A' | Triangle with output bubble | Rectangle with '1' and output bubble | ~9 ns (74HC04) |
| NAND | Q = (A · B)' | D-shape with output bubble | Rectangle with '&' and output bubble | ~12 ns (74HC00) |
| NOR | Q = (A + B)' | Shield shape with output bubble | Rectangle with '≥1' and output bubble | ~12 ns (74HC02) |
| XOR | Q = A ⊕ B | Shield shape with double curved back | Rectangle with '=1' inside | ~18 ns (74HC86) |
| XNOR | Q = (A ⊕ B)' | XOR shape with output bubble | Rectangle with '=1' and output bubble | ~18 ns (74HC266) |
Regional Standards: ANSI/IEEE vs. IEC 60617
Choosing which standard to apply depends on your region, your industry, and the specific documentation you are referencing. Neither is inherently 'more correct,' but mixing them on a single schematic is a cardinal sin of electrical drafting.
ANSI/IEEE Std 91/91A (Distinctive Shapes)
This is the dominant standard in North America, US military documentation (formerly MIL-STD-806), and university textbooks. It relies on the physical shape of the symbol to convey the logic function. The D-shape immediately tells you 'AND', while the curved shield shape means 'OR'. It is highly intuitive for beginners but becomes cluttered and difficult to parse in complex, high-density schematics like FPGA block diagrams.
IEC 60617-12 (Rectangular Outlines)
Mandated across the European Union and heavily adopted in international industrial automation (PLC ladder logic, SCADA HMI design). According to the IEC 60617 standard, all logic gates are drawn as identical rectangles. The function is defined entirely by the alphanumeric code inside the box (e.g., '&' for AND, '≥1' for OR). This makes automated schematic generation and dense IC pinout diagrams much cleaner, but requires the reader to memorize the internal codes rather than relying on visual shapes.
Rows People Get Wrong: Faded Markings and Misreads
When you are troubleshooting legacy equipment or reading poorly printed PDFs, certain boolean symbols degrade in ways that cause catastrophic misinterpretations. Here are the most common traps and how to verify them on the bench.
The Faded Inversion Bubble (AND vs. NAND)
The inversion bubble (the small circle denoting a logical NOT) is often the smallest printed element on a schematic. On older blueprint copies, this bubble frequently fades or is obscured by a crease. The Fix: Do not guess based on context. Power up the board and use a logic probe or a digital multimeter. If both inputs measure HIGH (>2.4V for 5V TTL/CMOS) and the output is HIGH, you are looking at an AND gate (e.g., 74HC08). If the output is LOW (<0.5V), it is a NAND gate (e.g., 74HC00). The internal transistor topology of a NAND gate sinks current differently, which a bench test will immediately reveal.
The Missing XOR Curve (OR vs. XOR)
In ANSI drafting, an XOR gate is drawn exactly like an OR gate, but with a second, detached curved line parallel to the input side. If the schematic was scanned at a low DPI or printed with low toner, that second curve vanishes, making an XOR look exactly like an OR gate. The Fix: Check the truth table behavior. Tie Input A to HIGH and Input B to LOW. If the output is HIGH, it could be either. Now, tie both inputs to HIGH. If the output drops to LOW, it is an XOR gate. An OR gate will remain HIGH. You can also check the IC part number printed on the physical chip; a 74HC86 is XOR, while a 74HC32 is OR.
IEC '1' vs. Buffer Confusion
In the IEC standard, a non-inverting buffer is represented by a rectangle with the number '1' inside. Technicians unfamiliar with IEC 60617 often mistake this '1' for a wire label, a pin number, or an AND gate (confusing the '1' with the boolean identity element). Always look for the input and output lines; if there is only one input and one output passing straight through a rectangle, it is a buffer, regardless of the internal text.
Boolean Symbols FAQ
What do the small circles (bubbles) mean on boolean logic symbols?
The small circle, universally known as an inversion bubble, represents a logical NOT operation. When placed on the output of a gate, it inverts the final result (turning an AND into a NAND). When placed on an input, it indicates that the gate triggers on a LOW signal (active-low) rather than a HIGH signal. In IEC standards, the bubble is sometimes replaced by a small triangle or a bar over the signal name, but the functional meaning remains identical: the logic state is inverted at that specific node.
How do I read boolean symbols on a PLC ladder logic diagram?
PLC ladder logic rarely uses the standalone ANSI/IEEE or IEC gate symbols you see on component-level schematics. Instead, boolean logic is represented by 'contacts' (inputs) and 'coils' (outputs) arranged on horizontal rungs. A normally open (NO) contact acts as an AND operation when placed in series, and an OR operation when placed in parallel branches. A normally closed (NC) contact represents a NOT operation. If you are looking at a PLC Function Block Diagram (FBD) rather than ladder logic, you will see the IEC 60617 rectangular symbols ('&', '≥1') used exclusively.
Why do some schematics use a triangle with a circle instead of a D-shape for a NOT gate?
The triangle with an output bubble is the standard ANSI/IEEE symbol for a NOT gate (inverter). The D-shape is strictly reserved for multi-input gates like AND. However, you will sometimes see a triangle without a bubble. This is not a NOT gate; it is a non-inverting buffer. Buffers do not change the logic state (1 in = 1 out), but they are used to increase current drive capability, isolate capacitive loads, or clean up degraded signal edges. For a deeper dive into how these physical gates are constructed at the transistor level, the logic gate tutorials at Electronics Tutorials provide excellent CMOS breakdowns.
