A truth table is the definitive lookup chart for digital logic. Just as an electrician uses an ampacity chart to determine wire size, an electronics engineer or hobbyist uses boolean expressions truth tables to determine the exact output state of a logic gate for every possible combination of inputs. Below is the complete, bookmark-friendly reference chart for standard 2-input logic gates, mapped to the ANSI/IEEE Std 91-1991 standard for graphic symbols and logic functions.
How to Read a Boolean Expressions Truth Table
Before wiring up a 74-series or 4000-series CMOS IC, you need to know how to read the chart below. The table is divided into input columns (typically A and B) and output columns for each gate type.
RESET on an ATmega328P), you must look at the NAND or NOR columns, as these output a 0 (LOW) when specific conditions are met. Using an AND gate column for an active-low reset will result in a bricked or unresponsive microcontroller state.
How modifier rows change the base value: In wire sizing, derating factors modify base ampacity. In boolean logic, "Don't Care" (X) states and inverted inputs act as your modifiers. When optimizing logic with a Karnaugh map, an X means the output can be either 1 or 0 without affecting the final system behavior. This allows you to group larger blocks of 1s, simplifying the physical boolean expression and reducing the total IC count on your PCB.
The Master Logic Gate Lookup Chart
The following table covers all standard 2-input boolean gates. Use Ctrl+F (or Cmd+F) to quick-jump to your specific gate type.
| Input A | Input B | AND | OR | NAND | NOR | XOR | XNOR |
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |
Note: A 1 represents a HIGH logic state (typically VCC, e.g., 5V or 3.3V), and a 0 represents a LOW logic state (GND, 0V). Actual voltage thresholds depend on the logic family (TTL vs. CMOS).
What the Truth Table Cannot Tell You
A boolean truth table is a mathematical abstraction. It assumes ideal, instantaneous switching. When you move from a textbook digital logic tutorial to the physical workbench, the truth table fails to warn you about physical limitations. Here is what you must check in the manufacturer's datasheet:
- Propagation Delay ($t_{pd}$): The output does not change the exact nanosecond the input changes. For a standard TI SN74HC08 (Quad 2-Input AND Gate), the typical propagation delay at 5V and 25°C is 18ns. In high-speed clock circuits, this delay causes race conditions that a truth table cannot predict.
- Fan-Out Limits: The table shows logical states, not current drive capability. A standard 74HC series output can typically source or sink only about 4mA to 6mA. If your boolean expression dictates a HIGH output, but you connect it to five LED indicators drawing 10mA each, the output voltage will droop below the valid HIGH threshold ($V_{IH}$), causing logic errors downstream.
- Floating Inputs: The table assumes inputs are firmly at 0 or 1. In physical CMOS circuits (like the 4000 series or 74HC series), leaving an input unconnected (floating) causes the gate to oscillate at high frequencies, drawing massive current and potentially destroying the IC. Always tie unused inputs to VCC or GND via a resistor.
- Setup and Hold Times: For sequential logic (flip-flops, not covered in simple combinational tables above), the data input must be stable for a specific number of nanoseconds before and after the clock edge. Violating this results in metastability, where the output hovers between 0 and 1.
Frequently Asked Questions
How do I convert complex boolean expressions to truth tables?
Break the expression down into intermediate steps. For an expression like $Y = (A \cdot B) + (\overline{C})$, create a column for $(A \cdot B)$ and another for $(\overline{C})$. Fill out the table row by row for all possible input permutations (which is $2^n$ rows, where $n$ is the number of variables). Finally, apply the outermost OR operation to your intermediate columns to get the final $Y$ output. For 3 variables (A, B, C), your table will have 8 rows (000 through 111).
What does "X" or "Don't Care" mean in a Karnaugh map truth table?
A "Don't Care" condition (denoted by X or d) represents an input combination that will never occur in your physical system, or an input state where the output simply doesn't matter to the rest of the circuit. When minimizing boolean expressions using Karnaugh maps, you can treat an X as either a 1 or a 0—whichever helps you form the largest possible grouping of adjacent cells. This results in simpler logic equations and fewer physical gates on your board.
Why does my physical logic gate output differ from the theoretical truth table?
If your physical circuit is not matching the chart above, you are likely dealing with one of three physical layer issues: 1) Floating inputs picking up electromagnetic interference (EMI) and toggling randomly. 2) Voltage threshold mismatches, such as driving a 5V TTL input with a 3.3V CMOS output (the 3.3V HIGH might not meet the TTL $V_{IH}$ minimum of 2.0V reliably under load). 3) Exceeding current limits, causing the output voltage to sag. Verify your physical voltages with a multimeter or logic analyzer, and ensure all unused gate inputs are tied to a defined logic rail.
