Boolean algebra symbols translate abstract logical operations into physical circuit schematics. Whether you are designing a digital logic circuit, programming an FPGA, or troubleshooting a legacy industrial control board, knowing how to read and write these symbols across different global standards is mandatory. Below is the complete reference table for the core logic gates, their algebraic expressions, and the physical integrated circuits (ICs) that implement them.
Complete Boolean Algebra & Logic Gate Symbol Reference
The table below maps the fundamental boolean operators to their standard schematic representations. The propagation delays listed assume a standard 74HC-series CMOS IC operating at 5.0V DC with a 50pF capacitive load.
| Gate Name | Boolean Expression | ANSI/IEEE Shape | IEC 60617 Shape | Common IC (74HC) | Typical Delay |
|---|---|---|---|---|---|
| AND | A · B or AB | D-shape (flat back) | Rectangle with '&' | 74HC08 (Quad 2-in) | ~11 ns |
| OR | A + B | Curved shield shape | Rectangle with '≥1' | 74HC32 (Quad 2-in) | ~12 ns |
| NOT (Inverter) | A̅ or A' | Triangle with bubble | Rectangle with '1' & bubble | 74HC04 (Hex) | ~8 ns |
| NAND | A · B̅ | D-shape with bubble | Rectangle with '&' & bubble | 74HC00 (Quad 2-in) | ~10 ns |
| NOR | A + B̅ | Curved shield with bubble | Rectangle with '≥1' & bubble | 74HC02 (Quad 2-in) | ~11 ns |
| XOR | A ⊕ B | Double-curved back D | Rectangle with '=1' | 74HC86 (Quad 2-in) | ~14 ns |
| XNOR | A ⊕ B̅ | Double-curved D + bubble | Rectangle with '=1' & bubble | 74HC266 (Quad 2-in) | ~16 ns |
Standard Variants: ANSI/IEEE vs. IEC 60617 vs. DIN
Unlike residential wiring color codes, logic symbols are not strictly divided by geographic borders, but rather by industry sector and legacy documentation. You will encounter three primary standards on the bench.
- ANSI/IEEE Std 91 (US/Military/Commercial): This is the most common standard in North American schematic captures and hobbyist platforms like KiCad or Altium. It uses distinct geometric shapes (D-shapes, shields, triangles) to represent logic functions. The primary advantage is instant visual recognition; an engineer can trace a signal path and identify an OR gate at a glance without reading text qualifiers.
- IEC 60617-12 (International/European): The IEC standard mandates rectangular boxes for all logic gates, using internal text qualifiers (like
&for AND,≥1for OR, and=1for XOR) to define the function. This standard is heavily favored in programmable logic (FPGAs, CPLDs) and industrial PLC ladder logic because rectangles scale cleanly to complex, multi-input functions and bus structures where unique shapes would become visually chaotic. - DIN 40700 (Legacy German/European): Now officially obsolete and superseded by IEC 60617, you will still find DIN symbols in vintage European industrial machinery, old automotive ECUs, and Cold War-era telecommunications gear. DIN used a mix of rectangles and semi-circles that look like a hybrid of ANSI and IEC. If you are reverse-engineering a 1980s Siemens control board, expect to see DIN variants.
The 'Rows People Get Wrong' Notes
Even experienced technicians misinterpret specific boolean algebra symbols and their schematic equivalents. Here are the most common pitfalls.
1. XOR vs. OR (The Missing Curve)
In ANSI/IEEE notation, an OR gate has a single curved back. An XOR gate has a double curved back (an extra arc spaced slightly away from the main gate body). On tightly packed, poorly printed schematics, this second line vanishes, leading technicians to replace a 74HC86 (XOR) with a 74HC32 (OR), which will completely break parity-checkers and adder circuits.
2. De Morgan's Equivalents and 'Negative' Logic
A NAND gate is logically identical to a 'Negative-OR'. According to De Morgan's Laws, NOT (A AND B) is identical to (NOT A) OR (NOT B). Schematic designers will sometimes draw a NAND gate using an OR-gate shape with bubbles on the inputs rather than a D-shape with a bubble on the output. Both represent the exact same boolean function, but the latter is used to indicate 'active-low' input logic, which confuses beginners who think they are looking at a broken OR gate.
3. The Apostrophe vs. The Overline
In formal boolean algebra, the NOT operation is denoted by an overline (A̅). However, in programming, SPICE netlists, and plain-text documentation, the overline is impossible to type, so an apostrophe (A') or an exclamation mark (!A) is used. When reading a netlist, remember that A'B means (NOT A) AND B, not a variable named A-prime.
Troubleshooting Faded Schematics & Unmarked Logic ICs
When repairing legacy hardware, you will eventually encounter a 14-pin DIP logic IC where the laser etching has been burned off by a failing power supply, or the schematic page is torn. Here is the bench procedure to identify the boolean function safely.
- Identify Power Pins: For standard 14-pin 7400-series or CD4000-series logic, Pin 14 is VCC (connect to +5V for 74HC, or up to +15V for CD4000) and Pin 7 is GND. Apply power through a current-limited bench supply set to 50mA to prevent magic smoke if the chip is internally shorted.
- Locate the Internal Gates: A 14-pin quad 2-input IC contains four independent gates. The pinout usually follows a standard U-shape pattern. For a 74HC00 (NAND), Gate 1 is pins 1, 2 (inputs) and 3 (output).
- Build a Truth Table with a Multimeter: Set your multimeter to DC Voltage. Tie the inputs to GND (Logic 0) or VCC (Logic 1) using a 1kΩ pull-up/pull-down resistor to prevent excessive current draw if you accidentally wire an output as an input. Read the output voltage. If the output reads high (near VCC) only when both inputs are high, you have an AND gate (74HC08). If it reads high when inputs differ, it is an XOR gate (74HC86).
- Check for Schmitt Triggers: If the output voltage seems to 'snap' sharply between 0V and 5V with heavy hysteresis, you might be holding a Schmitt-trigger variant (like a 74HC14 Hex Inverter). These are used for debouncing mechanical switches and filtering noisy signals.
For comprehensive pinout and electrical characteristics of legacy logic families, the Texas Instruments CMOS Logic Data Book remains the definitive bench reference, covering everything from standard 74HC to advanced BiCMOS variants.
Boolean Algebra Symbols FAQ
What is the boolean algebra symbol for NOT?
In formal mathematical boolean algebra, the NOT operation (logical negation) is represented by an overline placed above the variable, such as A̅. In plain text, programming languages (like C or Python), and hardware description languages (like Verilog), it is written using an apostrophe (A'), an exclamation mark (!A), or a tilde (~A). On a schematic, it is represented by a small circle, universally called a 'bubble', placed on the input or output wire of a logic gate.
How do you write XOR in boolean algebra?
The Exclusive-OR (XOR) operation is written using a circled plus sign: A ⊕ B. This symbol indicates that the output is true if and only if the inputs differ (one is true, the other is false). Do not confuse this with the standard OR operator (+), which outputs true if one or both inputs are true. In programming, XOR is typically represented by the caret symbol (^), which frequently causes confusion for hardware engineers transitioning to firmware development.
What does a bubble on a logic gate symbol mean?
A bubble (a small, unfilled or filled circle) on a logic gate symbol represents logical inversion (a NOT operation). If the bubble is on the output of an AND gate, it becomes a NAND gate. If the bubble is on an input, it indicates 'active-low' logic. This means the gate will trigger when the input signal drops to 0V (Ground) rather than when it rises to VCC. This is a critical distinction in microcontroller interrupt pins and reset lines.
Are IEC rectangular logic symbols still used today?
Yes, IEC 60617 rectangular symbols are heavily used in modern digital design, particularly in FPGA architectures, complex programmable logic devices (CPLDs), and industrial automation (PLC ladder logic). While hobbyists and discrete board designers still prefer ANSI/IEEE shapes for their visual distinctiveness, the IEC rectangular format scales much better for massive bus structures and complex macrocells where drawing unique shapes for every function would clutter the schematic beyond readability.






