Boolean Algebra Equations for Hardware Interlocks: Derivation and Bench Reality

On a whiteboard, boolean algebra is a clean, abstract system of ones and zeros. On the workbench, those ones and zeros are physical voltages pushing current through silicon gates. When you design a safety interlock or a motor-enable circuit using boolean algebra equations, you aren't just solving for Y; you are managing propagation delays, logic thresholds, and quiescent current draw.

This guide bridges the gap between abstract logic derivation and physical hardware implementation, using a standard 5V HC-CMOS logic family as our baseline.

The Core Boolean Equation for Hardware Interlocks

Let's derive a practical safety interlock equation for a workshop dust collector motor. The motor (Y) should only run if the main switch (A) AND the safety door switch (B) are closed, OR if the manual override (D) is engaged while the automated sensor (C) is NOT triggering a fault.

The governing boolean algebra equation is:

Y = (A · B) + (C' · D)

Here is the spec-sheet table defining every symbol, mapping the abstract math to physical bench realities for a standard 74HC series logic IC operating at 5.0V.

When this applies and its assumptions: This equation assumes purely combinational logic with no clock signals (no flip-flops). It assumes all inputs are strictly bound to defined logic levels (0V or 5V) and that the propagation delay of the gates (typically ~14ns for 74HC at 5V) is negligible compared to the mechanical response time of the motor contactor.

Rearranged Forms and Inverse Logic Conditions

A common trap for beginners is trying to "solve for X" in boolean algebra the same way they do in linear algebra. If Y = A + B, you cannot rearrange it to A = Y - B. Logical OR is not arithmetic addition. Instead, we use De Morgan's Theorems and necessary condition logic to rearrange forms.

Here are the valid rearranged forms for our interlock equation, useful for fault-finding and designing active-low emergency stop circuits:

• De Morgan's Inverse (Solving for NOT Y):
  Y' = (A' + B') · (C + D')
  Bench use: This tells you exactly how to wire an active-low safety shutdown relay. The relay drops out if A OR B fails, OR if C faults while D is off.
• Necessary Condition for Y = 1 (Path 1):
  If Y = 1 and D = 0, then it is strictly required that A = 1 AND B = 1.
• Necessary Condition for Y = 0 (Fault Isolation):
  If Y = 0, then (A · B) MUST be 0, AND (C' · D) MUST be 0.
  Bench use: If the motor won't start, and you measure D=1 (Override ON), you immediately know C must be 1 (Fault present), because if C were 0, C' would be 1, and Y would be 1.

Solved Bench Problems: Tracking Logic States and Voltage Units

Let's solve two problems tracking not just the unitless boolean states, but the physical voltage and current units on the bench.

Problem 1: Forward Evaluation with Current Draw

Given: Main switch A is closed (5V), Door B is open (0V), Sensor C is faulting (5V), Override D is engaged (5V). The 74HC32 OR gate has a quiescent current of 2 µA, and the output drives a 5V relay coil with a resistance of 250Ω.

1. Track Path 1 (A · B): 1 · 0 = 0 (0V).
2. Track Path 2 (C' · D): C is 1, so C' is 0. 0 · 1 = 0 (0V).
3. Final OR: 0 + 0 = 0 (0V at Y).
4. Physical Current Calculation: Since Y = 0V, the voltage across the 250Ω relay coil is 0V. I = V/R = 0/250 = 0 mA. The only current draw is the IC's quiescent 2 µA.

Outcome: Motor stays off. The door being open overrides the manual override.

Problem 2: Backward Fault Isolation

Given: The motor is running (Y = 1, measured at 4.9V). You verify the main switch A is OFF (A = 0, 0V). What must be the physical state of Override D?

1. Since A = 0, the term (A · B) is forced to 0, regardless of B.
2. The equation collapses to: Y = 0 + (C' · D), which simplifies to Y = C' · D.
3. We know Y = 1. For an AND gate to output 1, both inputs must be 1.
4. Therefore, C' = 1 AND D = 1.

Outcome: Override D must be physically engaged (5V), and Sensor C must be clear (0V). If D measures 0V on your multimeter, your OR gate is likely shorted internally or wired incorrectly.

Real-World Scenario: The Floating Input Catastrophe

The Numbers: VCC is a stable 5.01V. The disconnected input C floats to approximately 2.6V due to ambient electromagnetic noise and internal IC leakage.

The Outcome: The output Y oscillates wildly. The motor contactor chatters at roughly 60Hz, and the 74HC04 inverter chip becomes hot to the touch, drawing 18 mA instead of its normal 2 µA.

What Went Wrong (The Physics vs. The Math):
Boolean algebra strictly assumes C ∈ {0, 1}. It has no concept of 2.6V. However, physical CMOS gates have a linear region. For a 5V 74HC chip, the input threshold voltage (V_IH) is typically 3.15V, and the low threshold (V_IL) is 1.35V.

When input C sits at 2.6V, it is squarely in the undefined linear region. Both the PMOS and NMOS transistors inside the 74HC04 inverter turn on simultaneously. This creates a low-resistance path straight from VCC to GND, known as shoot-through current. This spikes the die temperature, causes thermal noise, and makes the output oscillate, which the OR gate happily passes to your motor relay. Always use 10kΩ pull-up or pull-down resistors on unused or potentially disconnected CMOS inputs.

Magnitude Checks and Unit Mistakes That Break the Math

When transitioning from paper to the bench, keep these realistic magnitudes and common unit mistakes in mind to ensure your 74HC logic gates behave as your equations predict.

What a Realistic Answer Magnitude Looks Like

• Voltage Thresholds (5V VCC): A logic "1" isn't exactly 5V. Anything above 3.15V is guaranteed HIGH. Anything below 1.35V is guaranteed LOW. Between 1.35V and 3.15V is the forbidden zone.
• Propagation Delay: When A and B transition HIGH, Y won't go HIGH instantly. Expect a delay of ~14 ns per gate at 5V. In a 3-gate series path, your total math-to-physics delay is ~42 ns.
• Output Current Limits: A standard 74HC gate can source or sink a maximum of ±4 mA per pin. If your relay coil requires 20 mA, the boolean equation is correct, but the hardware will fail. You must add a 2N2222 BJT or a ULN2003 Darlington array to buffer the Y output.

Unit Mistakes That Break the Circuit

1. Treating '+' as Arithmetic Addition: In boolean algebra, 1 + 1 = 1. If you map this to a DAC (Digital-to-Analog Converter) or an analog summing amplifier expecting 1V + 1V = 2V, your circuit will saturate or clip. Logical OR is a threshold operation, not an accumulation of voltage.
2. Mixing Active-High and Active-Low without Overbars: If your door switch B is wired as "Normally Closed" (5V when door is closed, 0V when open), your physical hardware is active-low. If your math assumes active-high, the motor will run when the door opens. You must update the equation to Y = (A · B') and add a physical inverter, or change the switch wiring.
3. Ignoring Fan-Out Limits: One boolean variable (like A) might feed into five different AND gates in a larger equation. While the math treats A as an infinite source of "1", a physical 74HC gate can only source ~4 mA. Five 74HC inputs draw roughly 5 µA total (well within limits), but if you are driving LEDs directly off that same node without buffering, the voltage will sag below the 3.15V V_IH threshold, causing downstream gates to read a "1" as a "0".

Boolean algebra equations give you the logical blueprint, but understanding the voltage units, current limits, and physical thresholds of your logic family is what keeps the magic smoke inside the ICs.