When designing discrete control logic for DC motor reversing or H-bridge driving, the most catastrophic failure mode is shoot-through: both the high-side and low-side (or forward and reverse) switches turning on simultaneously, shorting the power supply directly to ground. You cannot rely on software interlocks or human reflexes to prevent this. Hardware interlocking using integrated circuit logic gates is the only fail-safe method.
The direct answer for a robust, bench-testable interlocking circuit is a cross-coupled NAND latch built on a 74HC00 quad 2-input NAND IC. This topology guarantees that asserting one output physically forces the opposing output into a high-impedance or low state, regardless of switch bounce or simultaneous user input.
Logic Family Decision Path: Picking the Right IC
Before wiring the topology, you must select the correct logic family. Walking into a supplier or searching a distributor yields three common quad NAND options. Here is the decision matrix to terminate your part selection:
| Logic Family | Part Number | VCC Range | Pros & Cons | Verdict |
|---|---|---|---|---|
| Standard CMOS | CD4011B | 3V to 15V | Wide voltage, but slow propagation delay (~50ns) and weak output drive (~6mA). | Use only if VCC > 6V. |
| Legacy TTL | 74LS00 | 4.75V to 5.25V | Strict 5V only, high static power draw, obsolete architecture. | Avoid entirely. |
| High-Speed CMOS | 74HC00 | 2V to 6V | Low static power, fast switching (~15ns), symmetric 25mA drive. | Default Pick. |
Cross-Coupled NAND Topology and Node Map
Why use a cross-coupled NAND latch instead of simply wiring two independent AND gates with mechanical interlock switches? Independent gates lack memory; if a switch bounces or a user forces both mechanical buttons past their physical detents, both outputs can briefly go HIGH. A cross-coupled topology uses positive feedback to create a bistable state. Once Output Q goes HIGH, it feeds back into the opposing gate, physically locking Output /Q LOW until a deliberate reset command is issued.
Here is the topology mapped to the internal gates of the 74HC00 (Pins 1-6 for U1A, Pins 8-10 for U1B):
- Node A (/SET): Pin 1. Connected to the Forward momentary switch and a 10kΩ pull-up to VCC.
- Node B (/RESET): Pin 5. Connected to the Reverse momentary switch and a 10kΩ pull-up to VCC.
- Node Q (OUT_FWD): Pin 3. Output of U1A. Feeds back to Pin 4 (Input of U1B).
- Node /Q (OUT_REV): Pin 6. Output of U1B. Feeds back to Pin 2 (Input of U1A).
Because NAND gates output LOW only when both inputs are HIGH, pulling Node A to GND (pressing Forward) forces Node Q HIGH. This HIGH signal routes to Pin 4, ensuring that even if Node B is subsequently pulled LOW, Pin 4 remains HIGH, keeping Node /Q locked LOW. Shoot-through is mathematically impossible.
Behavior Matrix and Extreme Failure Modes
Understanding how the circuit behaves under normal and abnormal conditions is critical for debugging. The 74HC00 inputs are active-LOW. A switch press pulls the node to GND (Logic 0). An unpressed switch is pulled to VCC (Logic 1).
| SW_FWD (Node A) | SW_REV (Node B) | Node Q (FWD) | Node /Q (REV) | System Action |
|---|---|---|---|---|
| 1 (Released) | 1 (Released) | Previous State | Previous State | Motor holds last direction or idle. |
| 0 (Pressed) | 1 (Released) | 1 (HIGH) | 0 (LOW) | Motor runs Forward. |
| 1 (Released) | 0 (Pressed) | 0 (LOW) | 1 (HIGH) | Motor runs Reverse. |
| 0 (Pressed) | 0 (Pressed) | 1 (HIGH) | 1 (HIGH) | Forbidden State: Both outputs HIGH. Interlock defeated. |
What Breaks at the Extremes?
Logic gates are unforgiving of analog abuse. Here are the two most common bench failures and their physical mechanisms:
- The Floating Input (Open Pull-up): If your 10kΩ pull-up resistor on Node A fails open, or you forget to wire it, the CMOS input impedance is practically infinite (10^12 Ω). Stray electromagnetic noise will cause the input voltage to wander between the logic thresholds. The internal MOSFETs will rapidly toggle, creating a low-impedance path between VCC and GND inside the silicon. Result: The IC will draw tens of milliamps instead of microamps, overheat, and suffer thermal runaway within seconds.
- The Output Short (Node Q to GND): If you accidentally wire Node Q directly to a grounded chassis or a shorted relay coil, the IC attempts to source current. The SN74HC00 absolute maximum continuous output current is 25mA per pin. Result: The microscopic gold bond wire inside the DIP package fuses and vaporizes, permanently killing that specific gate while the other three gates in the package continue to work perfectly, leading to maddening debugging sessions.
Design Walkthrough: Sizing the Passives
A bare IC does not make a circuit. You must size the surrounding passives to protect the silicon and interface with the real world. Here are the exact component values for a 5V system driving a 12V DC motor via MOSFETs.
- Pull-up Resistors (R1, R2): 10kΩ. At 5V, a 10kΩ resistor limits switch current to 0.5mA. This is well below the rating of cheap tactile switches, prevents contact arcing, and is low enough to easily overcome the 1µA maximum leakage current of the HC inputs, ensuring a solid Logic 1.
- Bypass Capacitor (C1): 100nF (0.1µF) MLCC, X7R. Place this physically as close to Pin 7 (GND) and Pin 14 (VCC) as possible. When the outputs switch states, they draw transient current spikes. Without this local reservoir, the VCC rail will ring, potentially resetting adjacent microcontrollers.
- Output Indicator LEDs: 330Ω series resistors. If you want visual feedback on Node Q and /Q, use a standard 2V red LED. (5V - 2V) / 10mA = 300Ω. A 330Ω standard value limits current to ~9mA, safely under the 25mA pin limit, leaving headroom for the MOSFET gate drive.
- MOSFET Gate Drive: IRLZ44N with 100Ω gate resistor and 10kΩ gate-to-source pull-down. The 74HC00 outputs 5V, which is enough to fully enhance the logic-level IRLZ44N (Vgs(th) is 1-2V). The 100Ω series resistor damps high-frequency ringing on the gate trace, and the 10kΩ pull-down ensures the MOSFET stays off during the milliseconds while the 74HC00 is powering up and its outputs are in an undefined high-impedance state.
Step-by-Step Breadboard Verification
Do not apply power until you have verified the wiring. Follow this exact sequence to test the interlocked logic safely on a standard 830-tie-point solderless breadboard.
- Seat the IC: Straddle the center trench with the SN74HC00N. Ensure the notch faces left (Pin 1 is top-left, Pin 14 is top-right).
- Wire Power Rails: Connect Pin 14 to the positive (red) rail and Pin 7 to the negative (blue) rail. Do not apply power yet.
- Install the Bypass Cap: Insert the 100nF MLCC capacitor directly across the IC, with one leg in the same row as Pin 7 and the other in the row as Pin 14.
- Wire the Feedback Loop: Use short, bare jumper wires to connect Pin 3 (Node Q) to Pin 4, and Pin 6 (Node /Q) to Pin 2. This establishes the cross-coupled latch.
- Install Pull-ups and Switches: Place 10kΩ resistors from the positive rail to Pin 1 and Pin 5. Wire momentary tactile switches between Pin 1 and GND, and Pin 5 and GND.
- Add Output Indicators: Wire a 330Ω resistor from Pin 3 to the anode of a red LED (cathode to GND). Repeat for Pin 6 with a green LED.
- Pre-Flight Check: Set your multimeter to continuity mode. Verify there is no dead short between the red and blue power rails. Verify Pin 7 and Pin 14 are not swapped.
- Energize and Test: Apply 5.0V to the rails. Both LEDs should remain off (or one might randomly illuminate due to power-on metastability). Press the Forward switch; the Red LED must lock ON. Release it; it stays ON. Press the Reverse switch; the Red LED must snap OFF and the Green LED must lock ON. Pressing both simultaneously should result in both LEDs turning ON (the forbidden state), but releasing one will immediately resolve the latch back to a single active state.
For deeper theoretical background on CMOS input structures and why floating pins cause thermal runaway, refer to the All About Circuits guide on CMOS Logic Gates. For exact propagation delays and absolute maximum ratings, always consult the Texas Instruments SN74HC00 Datasheet before finalizing your PCB layout.
By standardizing on the 74HC00 and adhering to this cross-coupled topology, you eliminate software race conditions and guarantee hardware-level shoot-through protection for your motor drives.
