Boolean Algebra De Morgan's Law: Circuit Applications & Logic Simplification

De Morgan's Laws state that inverting the output of an AND gate yields the exact same logical result as an OR gate with inverted inputs, and conversely, inverting an OR gate yields an AND gate with inverted inputs. If you are designing digital circuits, writing PLC ladder logic, or configuring microcontroller interrupts, this theorem is the bridge between physical hardware constraints and the logical behavior you actually want. It allows you to swap gate types, optimize IC counts on a crowded PCB, and untangle messy relay logic without changing the final output.

The Core Mechanics and a Worked Numeric Example

To see how this works on the bench, let us look at the first theorem using real voltage values from a standard 5V CMOS logic family (like the 74HC series). We will evaluate both sides of the equation NOT (A AND B) = (NOT A) OR (NOT B) using specific binary inputs.

The Setup:

• Input A: Logic 1 (measured at 4.8V HIGH)
• Input B: Logic 0 (measured at 0.2V LOW)

Evaluating the Left Side: NOT (A AND B)

1. First, apply the AND operation: 1 AND 0 = 0.
2. Next, invert the result: NOT (0) = 1.
3. Final Output: 1 (HIGH / ~5V)

Evaluating the Right Side: (NOT A) OR (NOT B)

1. First, invert the individual inputs: NOT A = 0, and NOT B = 1.
2. Next, apply the OR operation to those inverted values: 0 OR 1 = 1.
3. Final Output: 1 (HIGH / ~5V)

Both paths yield a Logic 1. In a physical circuit, this means you can replace a single NAND gate (like a 74HC00) with an OR gate (74HC32) fed by two inverters (74HC04), or vice versa. While doing this with discrete ICs usually wastes board space, understanding this equivalence is critical when you run out of a specific gate type in a multi-gate package and need to repurpose the unused gates to finish a design.

Where You Meet This In Practice

You rarely sit down with a pencil to write out Boolean proofs on a jobsite, but De Morgan's Law dictates how you wire and program real-world control systems.

PLC Ladder Logic and Safety Circuits

In industrial automation (using platforms like Allen-Bradley Studio 5000 or Siemens TIA Portal), physical safety devices like Emergency Stop (E-Stop) buttons are wired normally closed (NC) for fail-safe operation. If the wire breaks, the circuit opens and the machine halts.

Suppose you have two NC E-Stops wired to digital inputs. To allow the motor to run, both E-Stops must be unpressed (meaning both inputs are receiving 24V, or Logic 1). The logical requirement to run is: NOT (EStop1_Pressed OR EStop2_Pressed). By applying De Morgan's Law, this translates to NOT EStop1_Pressed AND NOT EStop2_Pressed. In ladder logic, this means you place two Examine If Closed (XIC) instructions in series on the rung, rather than building a complex parallel branch with Examine If Open (XIO) instructions. It makes the rung easier to read and troubleshoot with a multimeter.

Microcontroller Active-Low GPIO Interrupts

When wiring pushbuttons to an ESP32 or STM32, we typically use external pull-up resistors. The GPIO pin rests at 3.3V (HIGH) and drops to 0V (LOW) when the button is pressed. This is an active-low configuration. If your software logic requires an action only when Button A AND Button B are pressed, the physical hardware is actually feeding you a NOR-like active-low signal. De Morgan's Law helps you map the physical voltage drops to the correct software interrupt flags (e.g., configuring GPIO_INTR_NEGEDGE and combining the states in your ISR).

FPGA and Verilog Synthesis Optimization

In hardware description languages like Verilog, synthesis tools use De Morgan's theorems to minimize the transistor count on the silicon. A designer might write assign out = ~(a & b); (a NAND operation), but the synthesis tool might map this to a NOR gate with inverted inputs on the FPGA fabric if that specific routing path yields a lower propagation delay. Understanding the law helps you read post-synthesis schematic reports without getting confused by the inverted bubbles.

Common Confusions and 'Bubble Pushing'

The most common mistake hobbyists and students make is forgetting to change the operator. When you break the inversion bar (the NOT operator) over a group of variables, you must flip the AND to an OR, or the OR to an AND. If you just distribute the NOT signs and leave the operator the same, you have accidentally applied the distributive law, which will completely break your logic.

On schematics, we use a technique called bubble pushing to visualize this. The inversion bubble on the output of a NAND gate can be 'pushed' back through the gate symbol, which changes the AND shape to an OR shape and places bubbles on the inputs.

Note: Always check the Texas Instruments Logic Portfolio or equivalent manufacturer datasheets for specific propagation delays (tpd) when substituting gates, as adding an inverter stage introduces a nanosecond-level delay that can cause race conditions in high-speed clocked circuits.

Frequently Asked Questions