A discrete transistor-based overcurrent protection circuit acts as a resettable electronic fuse. By using a sense resistor to trigger a shunt BJT, the circuit chokes the gate drive of a pass MOSFET the millisecond load current exceeds a set threshold. While modern 2026 designs often rely on dedicated e-fuse ICs like the TI TPS2596 series for commercial products, discrete topologies remain essential for high-voltage custom builds, repair bench projects, and understanding fundamental semiconductor behavior.
Topology and Node Definitions: The Low-Side N-FET Limiter
For DC systems under 30V, a low-side N-Channel MOSFET topology is vastly superior to a high-side P-Channel alternative. High-side P-FETs require careful gate-to-source clamping (usually via Zener diodes) to prevent gate oxide rupture during fast transients, and P-FETs inherently suffer from higher Rds(on) for the same silicon area. The low-side N-FET configuration references the gate drive to ground, making it inherently safer and cheaper to implement.
The circuit relies on four primary nodes:
- V_SUPPLY: The raw positive DC rail (e.g., 12V).
- V_DRAIN: The protected output node connecting to the load's ground return.
- V_SENSE: The feedback node between the MOSFET source and the sense resistor.
- GND: The common system ground.
The Current Path: Current flows from V_SUPPLY, through the Load, into V_DRAIN (Drain of Q1), out of the Source to V_SENSE, through R_sense, and finally to GND.
The Control Path: A 10kΩ pull-up resistor (R_gate) ties the Gate of Q1 to V_SUPPLY, turning the FET fully ON by default. The Base of the shunt NPN transistor (Q2) is tied to V_SENSE. Q2's Emitter is tied to GND, and its Collector is tied to the Gate of Q1.
When load current flows, a voltage drop appears across R_sense (V = I × R). Because Q2's Base-Emitter junction is a standard silicon PN diode, it remains off until V_SENSE reaches approximately 0.6V. Once the threshold is crossed, Q2 turns on, pulling Q1's Gate to GND and choking off the current.
Component Sizing and Stress Analysis
Let’s design this overcurrent protection circuit for a 12V nominal system with a strict 1.5A trip point. Using Ohm’s law, the sense resistor must drop 0.6V at 1.5A. Therefore, R_sense = 0.6V / 1.5A = 0.4Ω. The closest standard 1% resistor value is 0.39Ω, which yields an actual trip point of roughly 1.53A.
Below is the stress analysis and component selection matrix. This data is critical for ensuring the circuit survives the fault condition without catastrophic failure.
| Component | Designation | Value / Model | Rating | Stress at 1.5A Limit | Failure Consequence |
|---|---|---|---|---|---|
| Pass MOSFET | Q1 | IRLZ44N (Logic N-FET) | 55V, 47A | Vds = 11.4V, Id = 1.5A (P = 17.1W during fault) | Thermal runaway, silicon pop if unheatsinked |
| Sense Resistor | R_sense | 0.39Ω (Wirewound) | 3W, 1% | P = I²R = 0.87W continuous at trip | Resistor drifts open, load loses power |
| Shunt BJT | Q2 | 2N3904 (NPN) | 40V, 200mA | Ic ≈ 1.2mA (clamped by R_gate), Vce ≈ 0.2V | Fails short, Q1 gate held low permanently |
| Gate Pull-up | R_gate | 10kΩ (Carbon Film) | 0.25W | P = V²/R = 14.4mW (negligible) | Fails open, Q1 turns off, load dies |
Behavioral Matrix: Element Changes and Extremes
Understanding current limiting theory requires analyzing what happens when the protection itself fails. A robust design must fail safely. Here is how the topology reacts to extreme element alterations and component faults.
| Element Altered | Condition / Fault | Circuit Behavior | System Result |
|---|---|---|---|
| R_sense | Opens (trace breaks or thermal fuse blows) | Ground return path for load is severed; V_SENSE floats. | Load loses power completely. Safe failure mode. |
| R_sense | Shorts (solder bridge or internal failure) | V_SENSE is clamped to 0V. Q2 never receives Base bias. | Protection defeated. Q1 passes unlimited current until load or supply burns out. |
| Q2 (2N3904) | Base-Emitter junction shorts | Gate of Q1 is pulled directly to GND via Q2's Collector-Emitter path. | Q1 remains permanently OFF. Load is dead until Q2 is replaced. |
| Q1 (IRLZ44N) | Drain-Source shorts (thermal overstress) | MOSFET channel fuses into a low-resistance state, bypassing gate control. | Catastrophic failure. Full V_SUPPLY is applied to the load regardless of current draw. |
| Load | Dead short (0Ω across supply) | Current spikes, V_SENSE hits 0.6V in microseconds, Q2 clamps Gate. | Current limits to 1.53A. Q1 enters linear region and dissipates ~17W as heat. |
Thermal Reality: Safe Operating Area (SOA) Constraints
When the output is shorted, the overcurrent protection circuit does not "turn off" the power; it forces Q1 into its linear (active) region to drop the excess voltage. In a 12V system limited to 1.5A, Q1 must dissipate P = V × I = 11.4V × 1.5A = 17.1 Watts. A standard TO-220 package without a heatsink has a junction-to-ambient thermal resistance (RθJA) of roughly 62°C/W. At 17W, the silicon junction will rise by over 1,000°C per second, instantly exceeding the 175°C maximum junction temperature and destroying the FET. You must attach a heatsink rated for at least 5°C/W, or place a fast-acting 2A glass fuse in series with V_SUPPLY to clear prolonged dead-shorts.
Step-by-Step Breadboard Verification
Do not trust a protection circuit until you have intentionally abused it on the bench. Follow this verification sequence using a variable bench power supply and a digital multimeter (DMM).
- Cold Continuity Check (De-energized): Set your DMM to continuity mode. Verify that V_SUPPLY is not shorted to GND. Check that the Base of Q2 reads open to GND (you should see the diode drop of the B-E junction, roughly 0.6V, but not a dead short). Confirm R_sense reads exactly 0.39Ω.
- Quiescent Power-Up: Set the bench supply to 12.0V with a current limit of 3.0A. Connect V_SUPPLY and GND with no load attached. Measure V_DRAIN. It should read ~11.9V (accounting for the tiny voltage drop across the breadboard contacts and R_sense). V_SENSE should read 0.00V.
- Nominal Load Test: Connect a 10Ω, 5W power resistor across V_SUPPLY and V_DRAIN. Expected current is ~1.2A. Measure V_SENSE. It should read approximately 0.47V (1.2A × 0.39Ω). Because 0.47V is below the 0.6V Vbe threshold of Q2, the MOSFET remains fully enhanced, and Rds(on) stays near 22mΩ.
- Fault Injection (The Trip Test): Remove the 10Ω resistor. Connect a 2Ω, 10W power resistor. Without protection, this would draw 6A. With the circuit active, monitor V_SENSE with your DMM. The voltage will instantly clamp between 0.60V and 0.65V. The current will stabilize at roughly 1.53A. Carefully touch the tab of Q1—it will become painfully hot within 3 seconds, validating the SOA thermal warning above.
- Recovery Verification: Remove the 2Ω fault resistor and reconnect the 10Ω nominal load. The circuit should instantly recover without requiring a manual reset, as the BJT shunt naturally turns off when V_SENSE drops below 0.6V.
By mastering this discrete topology, you gain a foundational understanding of feedback loops and semiconductor limits that directly translates to debugging complex, integrated power management ICs on modern PCBs.
