A binary full adder circuit adds three 1-bit inputs (A, B, and Carry-In) to produce a 2-bit output (Sum and Carry-Out). While modern microcontrollers handle arithmetic in software, building a full adder in hardware is the foundational exercise for understanding propagation delay, race conditions, and logic gate fan-out. You can construct a 1-bit full adder using five discrete logic gates (two XORs, two ANDs, one OR) or use a dedicated integrated circuit like the 74HC283. Below is the exact topology, real component specifications, and a step-by-step guide to breadboarding and fault-finding the circuit.
Topology, Node Labels, and the Core Truth Table
The boolean logic for a full adder requires calculating the Sum and the Carry-Out ($C_{out}$) independently. The standard equations are:
- Sum = $A \oplus B \oplus C_{in}$
- $C_{out}$ = $(A \cdot B) + (C_{in} \cdot (A \oplus B))$
To map this to physical silicon, we define five internal nodes. This node map is critical when probing the circuit with a multimeter or logic analyzer:
- $N_1$ (XOR1 Output): $A \oplus B$
- $N_2$ (AND1 Output): $A \cdot B$
- $N_3$ (XOR2 Output / SUM): $N_1 \oplus C_{in}$
- $N_4$ (AND2 Output): $C_{in} \cdot N_1$
- $N_5$ (OR1 Output / COUT): $N_2 + N_4$
Standard Behavior Truth Table
| A | B | Cin | N1 (A⊕B) | N2 (A·B) | N4 (Cin·N1) | Sum (N3) | Cout (N5) |
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 |
| 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 |
Component Selection: Discrete 74HC Gates vs. Dedicated 74HC283
When designing this on a breadboard, you must choose between discrete gates and a dedicated adder IC. For educational purposes and fault-injection testing, the discrete 5-gate topology is superior. For any application requiring cascaded multi-bit addition (like an 8-bit ALU), the dedicated IC is mandatory to prevent massive wiring spaghetti and timing skew. We use the 74HC (High-Speed CMOS) family over the older 74LS (TTL) family because 74HC operates from 2.0V to 6.0V, draws significantly less quiescent current, and offers symmetric output drive.
| Parameter | Discrete 5-Gate Build (74HC86/08/32) | Dedicated IC (74HC283 4-Bit Adder) | Design Notes |
|---|---|---|---|
| IC Count (for 1-bit) | 3 ICs (using 5 of 12 available gates) | 1 IC (using 1 of 4 available bits) | Discrete wastes 7 unused gates; tie unused inputs to GND. |
| Total Pin Count | 42 pins across 3 DIP-14 packages | 16 pins (DIP-16 package) | Discrete requires significantly more breadboard real estate. |
| Max Propagation Delay (Sum) | ~42 ns (Cascaded: 14ns × 3 gates) | ~22 ns (Typical at 5V, 25°C) | Discrete Sum path passes through XOR1 → XOR2. |
| Max Propagation Delay (Cout) | ~68 ns (Cascaded: XOR → AND → OR) | ~22 ns (Carry-lookahead optimized) | The 74HC283 uses internal optimized carry logic. |
| Quiescent Power (Typ) | ~3 µA total (1 µA per IC at 5V) | ~1 µA total | Both are CMOS; power spikes only occur during switching. |
| Approx. Cost (2026) | $1.50 - $2.40 (for 3 generic DIPs) | $0.80 - $1.20 (single DIP) | Dedicated ICs are cheaper due to higher integration. |
Reference: For detailed timing diagrams and absolute maximum ratings, consult the Texas Instruments SN74HC86 datasheet and the SN74HC283 product page.
Fault Injection: What Breaks at the Extremes?
In a lab or troubleshooting environment, you need to know how the circuit behaves when a component fails. CMOS gates typically fail by shorting an output to VCC or GND, or by developing an internal open circuit. Here is the behavior table detailing what changes when specific elements fail.
| Fault Condition | Effect on Sum Output | Effect on Cout Output | Diagnostic Measurement |
|---|---|---|---|
| XOR1 (U1) Output Shorted to GND (Node $N_1$ stuck LOW) | Sum mirrors $C_{in}$ exactly. (Sum = $0 \oplus C_{in}$) | Cout ignores $C_{in}$, becomes purely $A \cdot B$. (Cout = $A \cdot B + 0$) | Probe U1 Pin 3. Reads 0V regardless of A/B switch states. |
| XOR1 (U1) Output Shorted to VCC (Node $N_1$ stuck HIGH) | Sum inverts $C_{in}$. (Sum = $1 \oplus C_{in}$) | Cout becomes $C_{in} + (A \cdot B)$. (Passes $C_{in}$ directly to OR gate) | Probe U1 Pin 3. Reads ~5V regardless of A/B switch states. |
| AND2 (U2) Output Open (Node $N_4$ floating) | Sum operates normally (unaffected by $N_4$). | Cout fails to trigger when $A \neq B$ and $C_{in}=1$. (Missing the $C_{in} \cdot N_1$ term) | Probe U2 Pin 6. Floating voltage (~2.5V) or erratic readings on DMM. |
| OR1 (U3) Input Shorted to VCC (Node $N_5$ stuck HIGH) | Sum operates normally. | Cout is permanently HIGH (LED always on). | Probe U3 Pin 3. Reads 5V constantly. Check for solder bridge or bent pin. |
Breadboard Walkthrough: Wiring and Testing Step-by-Step
Building this with discrete 74HC DIP ICs requires strict attention to power decoupling and input conditioning. Floating CMOS inputs will act as antennas, picking up ambient EMI and causing the outputs to oscillate wildly, which can overheat the IC.
Step 1: Power Rails and Decoupling
- Connect your bench power supply to the breadboard rails: +5V to the red rail, GND to the blue rail.
- Place the three ICs (74HC86, 74HC08, 74HC32) across the center trench.
- Wire Pin 14 of every IC to +5V and Pin 7 to GND.
- Critical: Place a 100nF (0.1µF) ceramic decoupling capacitor directly across Pin 7 and Pin 14 of each IC. This prevents voltage droop during simultaneous gate switching.
- Tie all unused gate inputs on the chips directly to GND. Never leave them floating.
Step 2: Input Conditioning
- Install three SPST momentary pushbutton switches for inputs A, B, and $C_{in}$.
- Wire one side of each switch to +5V.
- Wire the other side of each switch to the respective IC input pin.
- Install a 10kΩ pull-down resistor from each input pin to GND. This ensures the input reads a solid logic LOW (0V) when the switch is open.
Step 3: Gate Wiring (Follow the Node Map)
- U1 (74HC86 - XOR): Connect Switch A to Pin 1, Switch B to Pin 2. The output $N_1$ is on Pin 3.
- U2 (74HC08 - AND): Connect Switch A to Pin 1, Switch B to Pin 2. Output $N_2$ is on Pin 3. Then, connect $C_{in}$ to Pin 4, and $N_1$ (U1 Pin 3) to Pin 5. Output $N_4$ is on Pin 6.
- U1 (74HC86 - XOR, second gate): Connect $N_1$ to Pin 4, $C_{in}$ to Pin 5. The SUM output is on Pin 6.
- U3 (74HC32 - OR): Connect $N_2$ (U2 Pin 3) to Pin 1, and $N_4$ (U2 Pin 6) to Pin 2. The COUT output is on Pin 3.
Step 4: Output Buffering
- Connect a 330Ω current-limiting resistor to the SUM output (U1 Pin 6) and the COUT output (U3 Pin 3).
- Connect the anode (long leg) of a standard 5mm red LED to the resistor, and the cathode to GND. 74HC logic can source up to 25mA, but 330Ω limits current to ~10mA, ensuring long LED life and keeping the IC well within its thermal limits.
Verification, Switch Bounce, and Edge Cases
Once wired, reconnect the 5V supply. Verify the circuit by stepping through the truth table sequentially from 000 to 111. Press the switches in combination and confirm the LED states match the Sum and Cout columns.
The Switch Bounce Edge Case
If you transition from $A=1, B=1, C_{in}=0$ (Sum=0, Cout=1) to $A=0, B=0, C_{in}=0$ (Sum=0, Cout=0), you might notice the Cout LED briefly flickers or the Sum LED flashes. This is caused by mechanical switch bounce combined with propagation delay skew.
When you release two switches simultaneously, they don't open at the exact same microsecond. If Switch B opens slightly before Switch A, the circuit momentarily sees $A=1, B=0, C_{in}=0$, which yields Sum=1. Because the human eye can perceive flashes down to ~10ms, and switch bounce lasts 1-5ms, you will see a glitch.
How to fix it: For a clean, glitch-free bench demonstration, add a 100nF capacitor in parallel with each pull-down resistor (creating an RC low-pass filter with a ~1ms time constant), or replace the standard switches with a rotary DIP switch. For a production digital design, you would route the inputs through a Schmitt-trigger buffer (like the 74HC14) paired with a hardware debouncing flip-flop.
Building a binary full adder from discrete gates bridges the gap between abstract boolean algebra and physical electronics. By understanding the node topology, respecting CMOS decoupling requirements, and anticipating propagation skew, you gain the practical intuition required to design and debug much larger digital systems, such as the 8-bit breadboard computers documented in Ben Eater's hardware logic tutorials.
