All Logic Gates Truth Table: IC Selection & Voltage Thresholds

If you are designing a digital circuit, debugging a breadboard, or writing firmware that bit-bangs hardware logic, you need the definitive reference for binary states. The all logic gates truth table below maps the 7 fundamental logic operations (AND, OR, NOT, NAND, NOR, XOR, XNOR) to their exact boolean outputs. But a static table only tells half the story. To actually build a working circuit, you must pair this logic map with the correct integrated circuit (IC) family, accounting for voltage thresholds, propagation delay derating, and logic polarity.

The Master All Logic Gates Truth Table (IEEE Std 91-1984)

How to read this table: This chart follows the symbol and logic conventions established in IEEE Std 91-1984 (and IEC 60617-12). The Inputs (A, B) and Output (Y) columns represent standard positive logic, where a higher voltage (typically near $V_{CC}$) is a logical '1' and a lower voltage (near GND) is a logical '0'. The Standard 5V IC column provides the exact through-hole DIP part number for the classic 74HC (High-speed CMOS) family, which is the default choice for 5V hobbyist and bench work. The Standard 3.3V IC column maps to the 74LVC (Low-Voltage CMOS) family, required for modern microcontrollers like the ESP32 or Raspberry Pi.

Bookmark Quick-Jump: AND | OR | NOT | NAND | NOR | XOR | XNOR

Which Voltage Column Applies to Your Installation?

A truth table assumes ideal binary states, but physical silicon requires specific voltage thresholds to recognize a '1' or a '0'. The most common bench mistake I see is mixing 5V TTL (like the older 74LS series) with 5V CMOS (74HC series) or 3.3V microcontrollers. Here is how to determine which voltage column and logic family applies to your specific installation:

• 5V CMOS (74HC Family): Use this when your power supply is strictly 5.0V and you are interfacing with older Arduino Unos (ATmega328P) or 5V relays. The Input High Voltage ($V_{IH}$) threshold is typically 3.5V, and Input Low ($V_{IL}$) is 1.5V. Warning: A standard 74LS TTL chip only outputs a 'High' of about 2.7V, which will fail to trigger a 74HC CMOS input, resulting in a phantom logic low.
• 3.3V CMOS (74LVC / AUC Families): Mandatory if you are wiring logic gates to an ESP32, Raspberry Pi, or STM32. These ICs operate natively at 3.3V. The $V_{IH}$ threshold drops to roughly 2.0V. Feeding 5V into a 74LVC input without a level shifter will permanently damage the silicon gate oxide.
• Wide-Voltage CMOS (4000B Series): If your installation runs off a battery that sags from 12V down to 5V (like a 9V alkaline or a 12V lead-acid), use the CD4000B series (e.g., CD4011B for NAND). The truth table remains identical, but the voltage thresholds scale dynamically with $V_{DD}$.

Derating Logic: How Fan-Out and Temperature Modify the Base Value

The all logic gates truth table gives you a static, idealized output. However, datasheet derating rows modify the base timing and current values of that output based on environmental and electrical stress. While the logic state (1 or 0) doesn't change, when and how strongly that state arrives is heavily modified.

Here is how derating rows modify the base value in practice:

1. Voltage Derating (Propagation Delay): The base propagation delay for a 74HC08 AND gate is listed as 10ns at $V_{CC}$ = 5.0V. If your power supply sags and you run the chip at 3.3V (which is within its absolute maximum ratings), the internal transistors switch slower. The derating curve modifies your base value to roughly 18ns. If you are clocking data at 20MHz (50ns period), this 8ns shift could easily violate setup times on downstream flip-flops.
2. Capacitive Load Derating (Fan-Out): Every logic gate output has to charge the parasitic capacitance of the PCB traces and the inputs of the next gates. The base truth table assumes a 15pF load. If you wire one AND gate output to ten other inputs (high fan-out), the load might jump to 50pF. The derating row adds approximately 0.5ns per picofarad of extra load, modifying your base delay by an additional 17ns.
3. Temperature Derating: At the commercial maximum of 85°C, carrier mobility in the silicon drops. Expect propagation delays to increase by 15% to 20% over the room-temperature base value.

Decision Tree: Picking the Right Logic IC Family

Stop guessing which chip to add to your Mouser or DigiKey cart. Use this decision-tree-table to terminate your search with one concrete, purchasable part number based on your exact circuit constraints.

Default Recommendation: If you are building a general-purpose 5V breadboard prototype and just need to grab a handful of gates from your parts bin, buy the CD74HC08E (AND) and CD74HC00E (NAND) in DIP-14 packages. They are robust, tolerate minor power rail noise, and won't be destroyed by a brief static discharge from your fingers.

What the Truth Table Cannot Tell You

The all logic gates truth table is a map of steady-state boolean algebra. It is completely blind to the physics of time and transient states. When debugging a circuit that "should work according to the truth table" but is outputting garbage, check these three physical realities:

1. Floating Inputs and Oscillation: The truth table does not show what happens when an input is left unconnected (floating). In CMOS logic (74HC, 74LVC, 4000 series), a floating input acts as a high-impedance antenna. It will pick up ambient EMI, causing the internal transistors to rapidly toggle between high and low. This doesn't just cause erratic outputs; it causes massive internal shoot-through currents that will overheat and destroy the IC. Fix: Always tie unused CMOS inputs to GND or $V_{CC}$ with a 10kΩ resistor.
2. Metastability and Setup/Hold Times: If you are feeding a clocked logic gate (like a D flip-flop, which is built from the basic gates above), the truth table assumes inputs are stable before the clock edge. If your input changes exactly as the clock transitions, the gate enters a metastable state, outputting a voltage halfway between 0 and 1, or oscillating wildly until it randomly settles. The truth table has no row for "metastable."
3. Race Conditions and Glitches: Consider an AND gate where Input A goes from 1-to-0 and Input B goes from 0-to-1 simultaneously. The truth table says the output should remain 0. In reality, due to microscopic differences in silicon etching, Input B might turn on 2 nanoseconds before Input A turns off. This creates a brief, 2ns "glitch" (a logical 1) on the output. If that output is connected to a clock or interrupt pin, your microcontroller will trigger a phantom event.

By combining the theoretical certainty of the Texas Instruments Logic Portfolio truth tables with the physical realities of voltage thresholds and propagation derating, you can design digital logic circuits that work flawlessly on the bench and survive in the field.