When you add capacitance in series, the total equivalent capacitance of the circuit decreases. The governing formula is the reciprocal sum: 1/C_total = 1/C_1 + 1/C_2 + ... + 1/C_n. For two identical capacitors, the total capacitance is exactly half the value of one. While adding capacitors in parallel is the standard way to increase bulk energy storage, placing them in series serves entirely different engineering purposes: dividing AC voltage, blocking DC while passing high-frequency signals, and creating non-polarized capacitors from polarized electrolytics.

This guide breaks down the exact topology, failure modes, and bench-testing procedures you need to design reliable series capacitor networks, using real-world component values and measurements.

The Series Capacitor Topology: Node Labels and Core Behavior

To analyze a series capacitor network, we define three critical nodes in a basic two-capacitor string:

  • Node A (Input): The driven terminal of Capacitor 1 (C1).
  • Node B (Junction): The electrical connection point between C1 and Capacitor 2 (C2). This node is floating with respect to DC but carries the divided AC voltage.
  • Node C (Output/Ground): The grounded or load-facing terminal of C2.

Because the same AC current flows through both components, the voltage drop across each capacitor is inversely proportional to its capacitance (the smaller capacitor drops more voltage). The table below details exactly how the circuit behaves when you alter the physical parameters of the components.

Series Capacitor Behavior Matrix
Parameter Changed Effect on Total Capacitance (C_total) Effect on Node B Voltage (AC) Effect on Total Impedance (Z)
Increase C1 value Increases (approaches C2 value) Decreases (less voltage dropped across C1) Decreases
Decrease C1 value Decreases (approaches C1 value) Increases (more voltage dropped across C1) Increases
Increase AC Frequency No change (ideal) No change (ratio remains constant) Decreases (Z = 1 / 2πfC)
Add a third capacitor (C3) Decreases significantly Node B voltage splits across new nodes Increases
Bench Tip: Node B is a high-impedance floating node for DC. If you are probing Node B with a standard 10MΩ oscilloscope probe, the probe's input impedance will form an unintended RC high-pass filter with your capacitors, potentially skewing your low-frequency measurements. Use a 100:1 active probe or buffer Node B with a high-impedance op-amp (like the OPA140) for accurate readings.

Why Choose Series Over Parallel? (And When It Breaks)

Designers choose parallel topologies to maximize energy storage (C_total = C_1 + C_2) and lower Equivalent Series Resistance (ESR). You choose a series topology when your primary constraint is voltage rating or signal conditioning, not bulk storage. By placing two 250V capacitors in series, you can safely handle a 500V bus (provided you add high-value bleeder resistors to balance the DC leakage currents).

However, series configurations introduce unique failure modes that can silently destroy downstream circuitry. Understanding what breaks at the extremes is critical for robust design.

Failure Mode Contrast: Series vs. Parallel
Failure Type Result in Series Topology Result in Parallel Topology
C1 Fails Short C_total becomes C2. DC now passes directly to the load. If C2 cannot block the full DC bus, the downstream IC is destroyed. Dead short across the power rails. Blows the upstream fuse or causes a thermal event (smoke/fire).
C1 Fails Open C_total drops to zero. The signal path is completely broken. The circuit fails safe (no signal passes). C_total decreases by the value of C1. The circuit continues to operate with reduced filtering or higher ripple.
Dielectric Breakdown If C1 breaks down due to overvoltage, it usually shorts, passing full DC to C2, which then cascades into overvoltage failure. The shorted capacitor pulls the entire parallel bank down, usually tripping the power supply's overcurrent protection.

For a comprehensive look at how these topologies interact in complex AC networks, the All About Circuits textbook chapter on series RC networks provides excellent foundational math.

Design Walkthrough: Building a Precision AC Voltage Divider

Let's design a 50/50 AC voltage divider to step down a 10V peak-to-peak (Vpp) 1 kHz sine wave to 5V Vpp for an ADC input, while blocking a 12V DC offset. We need a total capacitance of roughly 100nF to keep the impedance low enough to drive a 10kΩ ADC input resistor without severe phase shift.

Target Specs:
C_total = 100nF
Voltage Rating: Must withstand at least 15V DC + 5V AC peak (20V total).

Component Selection:
We need two 200nF capacitors in series (200nF / 2 = 100nF). Do not use standard X7R MLCCs for precision AC division. X7R dielectrics exhibit a severe voltage coefficient of capacitance (VCC)—a 200nF X7R cap might drop to 120nF at 10V DC bias, ruining your 50/50 division ratio. Instead, we select C0G/NP0 dielectric capacitors, which have virtually zero VCC and temperature drift.

Real-World BOM:
Twox Murata GRM2195C1H204JA12D (200nF, 50V, C0G/NP0, 0805 package).
Cost: Approximately $0.18 per unit (total $0.36 for the divider).

  1. Calculate Impedance: At 1 kHz, the impedance of 100nF is Z = 1 / (2 * π * 1000 * 100e-9) = 1,591 Ω. This is well below the 10kΩ ADC input impedance, ensuring less than 15% signal attenuation from loading effects.
  2. Add Bleeder Resistors: Even in low-voltage AC coupling, parasitic leakage can cause Node B to drift. Add two 1MΩ resistors in parallel with C1 and C2 to force Node B to sit exactly at the midpoint of any DC bias.
  3. Verify Voltage Stress: With a 12V DC offset, C1 and C2 will each drop 6V DC (thanks to the 1MΩ balancing resistors). The 50V rating of the Murata parts provides a massive 8x safety margin, eliminating any risk of piezoelectric ringing or microphonic noise.

Step-by-Step Breadboard Testing Procedure

Before committing this divider to a PCB, validate the Node B behavior on the bench. You will need a function generator, a digital storage oscilloscope (DSO), and a known precision resistor (e.g., 10.0kΩ 1%).

  1. Assemble the Network: Insert the two 200nF C0G capacitors in series on the breadboard. Connect the junction (Node B) to your scope probe (Channel 2). Connect the input (Node A) to the function generator and Channel 1 of the scope.
  2. Establish the Baseline: Set the function generator to a 1 kHz sine wave, 10V Vpp, with a +5V DC offset. Verify on Channel 1 that the signal swings from 0V to +10V.
  3. Measure the Division: Observe Channel 2 (Node B). Because the capacitors block the +5V DC offset, you should see a 5V Vpp sine wave centered exactly at 0V (assuming your scope is set to AC coupling, or centered at the bias point if DC coupled with the bleeder resistors installed).
  4. Sweep for Phase Shift: Drop the frequency to 10 Hz. The impedance of the 100nF network rises to 159kΩ. If your scope probe is 10MΩ, the signal will pass, but if you add a 10kΩ load resistor from Node B to ground to simulate an ADC, the signal will attenuate heavily and shift in phase. Record the -3dB cutoff frequency.
  5. Induce a Fault: Power down. Use a jumper wire to short across C1. Power back up. Observe Channel 2. You will now see the full 10V Vpp signal, plus the +5V DC offset. This proves your failure mode analysis: a shorted series capacitor passes destructive DC to the load.
Safety Note: When testing series capacitor strings on high-voltage benches (e.g., >50V DC), always discharge Node B to ground with a grounded probe stick before touching the breadboard. The junction between series capacitors can retain a lethal or painful charge long after the power supply is turned off, as the dielectric absorption of the capacitors slowly bleeds charge back into the node.

For deeper mathematical modeling of parasitic inductance and ESR in series MLCC networks, refer to the Electronics Tutorials guide on capacitors in series, which covers the AC impedance vectors in detail.

Frequently Asked Questions

Does adding capacitance in series increase the voltage rating?

Yes, theoretically. Placing two identical 25V capacitors in series allows the string to withstand up to 50V. However, this only holds true if the voltage divides equally. In reality, manufacturing tolerances and differences in DC leakage current will cause one capacitor to drop more voltage than the other, potentially exceeding its individual rating. To safely increase voltage ratings in series, you must place high-value balancing (bleeder) resistors in parallel with each capacitor to force equal voltage distribution.

Why do my series capacitors measure lower than the calculated value?

If you measure two 100nF capacitors in series and your LCR meter reads 42nF instead of the expected 50nF, you are likely encountering the Voltage Coefficient of Capacitance (VCC) or probe loading. Class II dielectrics (like X7R and Y5V) lose significant capacitance when a DC bias is applied, even the small bias voltage output by some LCR meters. Furthermore, breadboard parasitic capacitance (typically 2pF to 5pF per contact) and the input capacitance of your meter probe (often 15pF) will skew measurements of small series networks. Always measure the individual components first, then verify the assembled network under actual operating AC conditions.

Can I add capacitance in series for DC power supply filtering?

No. Series capacitors block DC current. If you place capacitors in series on a DC power rail, you will create an open circuit for DC, preventing power from reaching your load. For DC power supply filtering and bulk energy storage, you must always use a parallel topology to lower the overall impedance and increase the total microfarad (µF) rating to smooth out voltage ripple.