Applying the Absorption Law Boolean to Optimize Discrete Logic and FPGAs

The Boolean absorption law states that a logic variable combined with its own conjunction or disjunction with another variable simplifies entirely back to the original variable, effectively absorbing the redundant term. In a physical circuit, applying this law changes the hardware by eliminating unnecessary logic gates, which directly reduces propagation delay, lowers quiescent power draw, and shrinks the physical PCB footprint. When you are designing a digital system—whether wiring discrete 7400-series ICs on a breadboard or writing RTL for an FPGA—failing to apply this law results in bloated designs that waste silicon, current, and nanoseconds.

The Core Math and a Real-World Hardware Example

The absorption law manifests in two primary algebraic forms:

• OR Absorption: A + (A · B) = A
• AND Absorption: A · (A + B) = A

To understand the physical impact, let us look at a numeric hardware example. Suppose you are designing a safety interlock for an industrial water pump. The pump should run if the primary pressure sensor is OK (P), OR if the pressure is OK AND the secondary temperature sensor is OK (T).

The unoptimized Boolean expression is: Y = P + (P · T)

Now, we apply the OR absorption law. Since P + (P · T) simplifies directly to P, the temperature sensor input is mathematically redundant to the final output state. If P is HIGH, the output is HIGH regardless of T. If P is LOW, the AND gate outputs LOW, and the OR gate outputs LOW regardless of T.

By applying the absorption law, you eliminated two ICs, saved $0.90 on the BOM, and shaved 28 nanoseconds off the system's reaction time. For high-speed digital circuits, 28 ns is the difference between a stable clock edge and a metastability failure.

Where You Meet This in Practice

You will encounter the need for Boolean absorption across three main domains in electrical and electronic engineering:

1. Discrete Logic and Legacy Board Repair

When reverse-engineering or repairing legacy industrial control boards, you will often find custom ASICs or PALs (Programmable Array Logic) that have gone obsolete. Replacing these with standard 74HC or 74LS glue logic requires you to extract and minimize the Boolean equations. Applying absorption keeps your replacement circuit small enough to fit in the original DIP footprint without requiring a daughterboard.

2. FPGA and CPLD Synthesis (Verilog/VHDL)

Modern synthesis tools like Xilinx Vivado or the open-source Yosys will automatically apply the absorption law during the logic optimization phase, mapping your RTL code into Look-Up Tables (LUTs). However, writing unabsorbed code (e.g., assign out = a | (a & b);) creates simulation-to-synthesis mismatches if your testbench relies on the exact gate-level delays of the unoptimized netlist. Writing clean, pre-absorbed RTL (assign out = a;) ensures your behavioral simulation perfectly matches the routed silicon.

3. PLC Ladder Logic Programming

In Programmable Logic Controllers (like Allen-Bradley MicroLogix or Siemens S7-1200), ladder logic is scanned sequentially. A typical PLC scan cycle is 1 to 10 milliseconds. If you program unabsorbed redundant branches into a complex safety rung, the PLC processor wastes scan time evaluating instructions that do not change the outcome. In high-speed packaging machines, bloated ladder logic can push the scan time past the I/O update window, causing missed sensor pulses.

Common Confusions: Absorption vs. Idempotent and Consensus

Makers and engineering students frequently confuse the absorption law with two other Boolean theorems. Knowing the difference prevents algebraic errors when minimizing complex Karnaugh maps.

Law / Theorem	Boolean Expression	Key Distinguishing Feature
Absorption	A + (A · B) = A	Involves one variable absorbing a term that contains itself AND another variable.
Idempotent	A + A = A / A · A = A	Involves only one single variable repeated. No second variable (like B) is present.
Consensus	AB + A'C + BC = AB + A'C	Involves three terms and a complemented variable (A and A'). The third term (BC) is the redundant consensus term.

The most common mistake is attempting to apply absorption to a consensus problem. If you see a complemented variable (like A' or ¬A), you are likely dealing with the Consensus Theorem, not Absorption. For a deeper mathematical breakdown of these rules, refer to the comprehensive guides on Electronics Tutorials' Boolean Algebra Laws.

Decision Tree: Optimizing Your Next Digital Logic Build

When your simplified Boolean equation is ready for physical implementation, use this decision path to select the correct hardware platform. Do not default to a massive FPGA for a simple absorbed glue-logic task, and do not use discrete ICs for a 64-bit state machine.

IF your absorbed logic requires...	THEN your optimal architecture is...	CONCRETE PART PICK (2026 Standard)
1 to 4 basic gates (AND, OR, NOT) with simple I/O voltages (3.3V or 5V).	Discrete CMOS Logic ICs. Lowest NRE (Non-Recurring Engineering) cost, instant prototyping.	Nexperia 74HC Series (e.g., 74HC00, 74HC32). Avoid older 74LS (bipolar) due to high power draw.
10 to 50 gates, or a simple state machine requiring registered outputs and flip-flops.	SPLD (Simple Programmable Logic Device). Replaces dozens of discrete ICs with one DIP/SOIC chip.	Microchip ATF22V1C (ATF series). 5V tolerant, EEPROM-based, no volatile configuration memory needed.
> 50 gates, high-speed parallel processing, or complex DSP math alongside control logic.	FPGA (Field Programmable Gate Array). Synthesizer will map absorbed logic into 4-input LUTs.	Lattice iCE40UP5K-SG48I. Ultra-low power, hard I2C/SPI blocks, supported by open-source Yosys toolchain.

For the vast majority of hobbyist and light-industrial sensor interlocks, the Nexperia 74HC series is the default pick. It offers the best balance of wide availability, low quiescent current, and 5V/3.3V compatibility.

FAQ: Boolean Simplification on the Bench

Bench Rule of Thumb: Before you wire a single jumper on the breadboard or compile a single line of Verilog, write out your Boolean equation and check for A + AB patterns. The cheapest, fastest, and most reliable logic gate is the one you completely eliminate from the design.