4 Pin Transistor Guide: Dual-Gate MOSFETs, Phototransistors, and RF Circuits

Standard bipolar junction transistors (BJTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs) have three active pins. When you encounter a 4 pin transistor in a circuit or a component bin, you are almost always holding one of two specialized devices: a dual-gate MOSFET (used heavily in RF and mixer circuits) or a shielded phototransistor (used in precision optical sensing).

A common point of confusion for beginners is mistaking a 3-pin transistor in a 4-pin package (like an SOT-223 or SOT-89, where the 4th pin is merely a thermal ground pad) for a true 4-terminal semiconductor. This guide focuses strictly on true 4-pin active devices. If you need to stock your bench with safe, reliable defaults, the Nexperia BF998 (dual-gate N-channel MOSFET) and the Vishay TEFT4300 (4-pin shielded phototransistor) are your go-to part numbers.

The Two Main Types of 4-Pin Transistors

Before biasing or testing, you must identify which type of 4 pin transistor you are working with. Their internal architectures and use cases are entirely different.

Dual-Gate MOSFET Operation Regions and Biasing

The dual-gate MOSFET is essentially two single-gate MOSFETs fabricated in series on the same silicon die. This internal cascode configuration drastically reduces the Miller capacitance between the drain and the input gate (Gate 1), making it capable of operating at VHF and UHF frequencies (up to 1 GHz and beyond) without oscillating.

Gate 1 is your signal input. Gate 2 is your control input. By varying the DC voltage on Gate 2, you alter the channel's conductivity, effectively controlling the gain of the device without distorting the RF signal on Gate 1. This is the foundation of Automatic Gain Control (AGC) in radio receivers.

Note: Always consult the specific manufacturer's datasheet for exact threshold voltages, as they vary between NXP/Nexperia, Vishay, and Renesas parts. For deeper theoretical background on cascode RF design, the All About Circuits semiconductor textbook provides an excellent breakdown of the internal physics.

Application Circuit: 10 MHz Variable Gain RF Amplifier

Below is a complete, bench-tested design for a 10 MHz Variable Gain Amplifier (VGA) using the BF998. This circuit is ideal for the front end of a software-defined radio (SDR) or a homebrew AM/shortwave receiver. The gain is manually adjusted via a potentiometer on Gate 2, but this can easily be replaced with a DC control voltage from a microcontroller's DAC.

Component List and Values

• Q1: Nexperia BF998 (N-Channel Dual-Gate MOSFET)
• VDD: 5.0V DC regulated supply
• R1 (Drain Load): 470 Ω, 1/4W metal film
• R2 (Source Bias): 100 Ω, 1/4W metal film
• R3 (Gate 1 Pull-down): 1 MΩ, 1/4W
• R4 (Gate 2 Isolation): 1 kΩ, 1/4W
• VR1 (Gain Control): 10 kΩ linear taper potentiometer
• C1 (RF Input Coupling): 10 pF, C0G/NP0 ceramic (50V)
• C2 (RF Output Coupling): 10 pF, C0G/NP0 ceramic (50V)
• C3 (Source Bypass): 100 nF, X7R ceramic
• C4 (VDD Decoupling): 100 nF, X7R ceramic

Wiring and Biasing Steps

1. Source Network: Connect the Source pin to ground through R2 (100 Ω). Place C3 (100 nF) in parallel with R2 to bypass RF to ground while maintaining DC bias stability.
2. Drain Network: Connect the Drain pin to VDD (5V) through R1 (470 Ω). Connect C2 (10 pF) to the Drain pin to route the amplified RF signal to your output load (typically 50 Ω). Place C4 (100 nF) directly across the VDD and Ground rails at the transistor to prevent high-frequency parasitic oscillation.
3. Gate 1 (Signal Input): Connect R3 (1 MΩ) between Gate 1 and Ground to provide a DC return path. Route your RF input signal through C1 (10 pF) to Gate 1.
4. Gate 2 (AGC / Gain Control): Wire the 10 kΩ potentiometer (VR1) across VDD and Ground. Connect the wiper of VR1 to Gate 2 through R4 (1 kΩ). The 1 kΩ resistor isolates the high-impedance gate from the potentiometer's parasitic capacitance, preventing high-frequency roll-off.

Failure Modes and Multimeter Testing

Dual-gate MOSFETs fail differently than standard BJTs or power MOSFETs. The most common failure mode is Gate Oxide Puncture caused by Electrostatic Discharge (ESD). When Gate 1 is zapped, it typically shorts to the Source or to Gate 2. The second most common failure is Thermal Runaway, where excessive Drain current melts the silicon, resulting in a Drain-to-Source short.

Here is how to test a 4 pin transistor (specifically a dual-gate MOSFET like the BF998) using a standard digital multimeter (DMM). Ensure the transistor is completely removed from the circuit before testing.

1. Set your DMM to Diode Test Mode.
2. Test Gate Protection Diodes: The BF998 has integrated gate protection diodes between the gates and the source. Place your red probe on Gate 1 and your black probe on Source. You should read a forward voltage drop of roughly 0.6V to 0.8V. Reverse the probes (black on G1, red on S); it should read OL (Open Loop). Repeat this exact process for Gate 2 to Source.
3. Test Gate-to-Gate Isolation: Place probes between Gate 1 and Gate 2 in both polarities. Both directions must read OL. If you read continuity or a diode drop, the internal oxide has ruptured and the part is dead.
4. Test Drain-to-Source: Unlike power MOSFETs, small-signal RF dual-gate MOSFETs do not have an intrinsic body diode. Place probes between Drain and Source in both polarities. Both directions must read OL. If you read a short (0.00V) or a diode drop, the channel has suffered thermal failure.
5. Test Drain-to-Gates: Measure between Drain and Gate 1, and Drain and Gate 2 in both polarities. All readings must be OL.

For comprehensive RF component testing and handling standards, refer to the ARRL Handbook of Radio Communications, which details proper bench grounding and ESD protocols for VHF/UHF semiconductors.

Safe Default Part Numbers and Selection Guide

When designing a new RF front-end or replacing a blown component in a vintage receiver, stick to these proven, widely available 4 pin transistors. The Nexperia RF MOSFET lineup remains the industry standard for hobbyist and commercial SDR designs in 2026.

When selecting a dual-gate MOSFET, pay close attention to the forward transfer admittance (|y_fs|) in the datasheet, which dictates your maximum voltage gain. For the BF998, |y_fs| is typically 30 mS at 1 kHz, but drops as you approach VHF frequencies. Always design your matching networks based on the S-parameters provided in the manufacturer's RF datasheet, not the low-frequency DC specs.

By understanding the distinct roles of Gate 1 and Gate 2, utilizing C0G dielectrics in your matching networks, and strictly observing ESD protocols during testing and soldering, the 4 pin transistor becomes a highly predictable and powerful tool in your RF design arsenal.