Designing a 3-Input Boolean Logic Circuit for Motor Interlocks

To build a reliable 3-input boolean logic circuit for an industrial interlock—where a motor runs only if a master enable is HIGH and at least one of two safety doors is closed—use the factored topology Y = A · (B + C) implemented with 74HC08 (AND) and 74HC32 (OR) CMOS ICs. This configuration minimizes IC count, guarantees rail-to-rail voltage swings at 5V, and provides predictable failure modes when integrated with physical limit switches.

Topology and Node Definitions: The Factored Approach

When designing a combinational boolean logic circuit, you can express the same logical outcome in multiple ways. For our interlock, the system requires Input A (Master Enable) to be HIGH, AND either Input B (Door 1 Closed) OR Input C (Door 2 Closed) to be HIGH.

We define the circuit nodes as follows:

• Node A: Master Enable switch (Active HIGH).
• Node B: Door 1 limit switch (Active HIGH).
• Node C: Door 2 limit switch (Active HIGH).
• Node D: Intermediate output from the OR gate (evaluates B + C).
• Node Y: Final output from the AND gate (evaluates A · D).

Why This Topology Over the Alternative?

Boolean algebra allows us to expand this expression into Y = (A · B) + (A · C). While logically identical, the expanded form requires two AND gates and one OR gate. If you are using standard 14-pin DIP ICs (which contain four 2-input gates each), the expanded form forces you to use three separate IC packages if you run out of gates, or heavily cross-wire a single package. The factored topology Y = A · (B + C) requires exactly one AND gate and one OR gate. This fits easily into two ICs (a Texas Instruments SN74HC08 and a SN74HC32), leaving six spare gates for future debouncing or indicator logic on the same breadboard.

Behavior Table: Node States and Voltages

The following table maps every possible input combination to the intermediate Node D and final Node Y. Voltages assume a 5.0V VCC supply and ideal CMOS rail-to-rail outputs.

Component Selection and Real-World Values

Choosing the right logic family is critical for physical circuits. While older 74LS (TTL) series chips are common in vintage kits, they draw high quiescent current and have asymmetric output swings (a 'HIGH' output might only reach 3.4V). For modern DIY and industrial prototyping, the 74HC (High-speed CMOS) family is the standard.

Failure Mode Contrast: What Breaks at the Extremes?

Logic simulators assume perfect 0V and 5V states. On the bench, physical wiring fails. Understanding how the Y = A · (B + C) topology degrades helps you design safer systems.

The Floating Input (Open Pull-Down Resistor)

If the 10kΩ pull-down resistor on Node B fails open, and the Door 1 switch is also open, Node B becomes floating. For a 74HC IC at 5V, the guaranteed LOW threshold ($V_{IL}$) is 1.35V, and the HIGH threshold ($V_{IH}$) is 3.15V. A floating pin will drift into the 1.5V–2.5V indeterminate region. Inside the IC, this causes both the PMOS and NMOS output transistors of that gate to partially turn on simultaneously—a condition called shoot-through. The IC will draw 10mA to 20mA of quiescent current (instead of microamps), heat up, and the output (Node D) may chatter erratically.

Short to VCC vs. Short to GND

• Node C shorts to VCC (5V): The OR gate sees a permanent HIGH. Node D becomes permanently HIGH. The circuit degrades from a 3-input interlock to a 1-input interlock (Motor runs whenever Master Enable A is closed). This is a fail-unsafe condition if Door 2 was meant to be a critical safety barrier.
• Node A shorts to GND (0V): The AND gate sees a permanent LOW. Node Y is forced LOW regardless of B or C. The motor can never start. This is a fail-safe condition, halting operations until the fault is cleared.

Step-by-Step Breadboard Testing Procedure

Follow this sequence to build and verify the circuit. Rushing the power connections is the most common cause of dead CMOS ICs.

1. Establish Power Rails: Connect your bench power supply to the breadboard's main rails. Set the supply to exactly 5.0V (the absolute maximum rating for 74HC is 6.0V, but 7.0V will instantly destroy the silicon). Verify with a multimeter before inserting ICs.
2. Seat the ICs: Place the 74HC32 (OR) and 74HC08 (AND) across the center trench. Ensure the notch or dot indicating Pin 1 faces the top-left. Pin 14 is VCC; Pin 7 is GND for both chips.
3. Wire Power and Decoupling: Connect Pin 14 to the +5V rail and Pin 7 to the GND rail for both ICs. Immediately place a 100nF ceramic capacitor across the VCC and GND pins of each IC, keeping the leads as short as possible.
4. Install Pull-Downs and Switches: Insert three 10kΩ resistors, tying one end to the GND rail. Connect the other ends to your SPST toggle switches. The other side of the switches goes to +5V. Wire the switch junctions to the input pins: Switch A to 74HC08 Pin 1, Switch B to 74HC32 Pin 1, Switch C to 74HC32 Pin 2.
5. Route the Intermediate Node: Connect the OR gate output (74HC32 Pin 3, Node D) to the second input of the AND gate (74HC08 Pin 2).
6. Wire the Output: Connect the final AND gate output (74HC08 Pin 3, Node Y) to a 470Ω resistor, then to the anode of your LED. Connect the LED cathode to GND.
7. Verify Logic States: Power on the supply. Test all 8 combinations from the behavior table. If the LED lights up on row 2 (A=0, B=0, C=1), your pull-down on Node A is likely missing or broken, allowing the AND gate to read a floating HIGH.

By adhering to the factored topology and respecting the physical realities of CMOS thresholds, you transform abstract boolean equations into a robust, noise-immune hardware interlock ready for integration with higher-power driver stages.