A multiplexer (MUX) acts as a digitally controlled switch, routing one of several input signals to a single output line. While you can buy integrated multiplexer chips off the shelf, building a multiplexer circuit diagram from discrete logic gates is the definitive way to understand the underlying Boolean topology, propagation delays, and failure modes. The standard 2-to-1 digital multiplexer relies on the Boolean expression Y = (A · S') + (B · S), where A and B are data inputs, S is the select line, and Y is the output.
Below is a complete design walkthrough using 74HC-series discrete logic, including exact component values, node mapping, failure analysis, and a step-by-step breadboard verification procedure.
Discrete 2-to-1 Multiplexer Topology and Node Labels
To build this circuit on a workbench, we translate the Boolean expression into physical gates using three standard DIP ICs from the Texas Instruments SN74HC family. We operate at a nominal 5V VCC, which guarantees standard TTL/CMOS compatibility and a typical propagation delay of 15ns per gate.
Component Selection and Values
- U1 (Inverter): 74HC04 (Hex Inverter). We use one gate to generate
S'(NOT Select). - U2 (AND Gates): 74HC08 (Quad 2-Input AND). We use two gates to generate the masked data paths.
- U3 (OR Gate): 74HC32 (Quad 2-Input OR). We use one gate to combine the masked paths.
- Input Pull-downs: 10kΩ resistors on inputs A, B, and S to prevent floating CMOS nodes.
- Bypass Capacitors: 100nF (0.1µF) X7R ceramic capacitors placed physically adjacent to the VCC/GND pins of every IC.
Node Label Mapping
When drafting or tracing the multiplexer circuit diagram, label your nets explicitly to isolate faults during testing:
- Node S: Select input (0 = route A, 1 = route B).
- Node A: Data Input 0.
- Node B: Data Input 1.
- Node N1: Output of U1A (Inverted S, or
S'). - Node N2: Output of U2A (
A AND N1). - Node N3: Output of U2B (
B AND S). - Node Y: Output of U3A (
N2 OR N3). This is your final MUX output.
Behavior Matrix and Failure Mode Contrast
Understanding what happens when the circuit operates normally is only half the battle; knowing how it fails at the extremes separates hobbyists from engineers. Below is the behavior matrix tracking every internal node.
| S (Select) | A (In0) | B (In1) | N1 (S') | N2 (A·S') | N3 (B·S) | Y (Out) | What Changes / Routed Path |
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | A is routed (A=0) |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 | A is routed (A=1) |
| 0 | 0 | 1 | 1 | 0 | 0 | 0 | A is routed (A=0, B ignored) |
| 0 | 1 | 1 | 1 | 1 | 0 | 1 | A is routed (A=1, B ignored) |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | B is routed (B=0, A ignored) |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | B is routed (B=0, A ignored) |
| 1 | 0 | 1 | 0 | 0 | 1 | 1 | B is routed (B=1) |
| 1 | 1 | 1 | 0 | 0 | 1 | 1 | B is routed (B=1) |
What Breaks at the Extremes?
If the wire connecting to Node S breaks or is left unconnected, the CMOS input of the 74HC04 acts as a high-impedance antenna. It will pick up ambient 50/60Hz electromagnetic noise. Node N1 will oscillate rapidly, causing both N2 and N3 to pass data unpredictably. The output Y will glitch or lock up. Fix: Always use a 10kΩ pull-down or pull-up resistor on CMOS select lines.
If a solder bridge or stray wire shorts Node N2 to GND, the
A input path is permanently disabled. When S=0, N2 should pass the state of A to Y. With N2 shorted, Y will remain stubbornly LOW (0) regardless of what logic level you apply to input A. The circuit will only function correctly when S=1 (routing B).
Discrete Logic vs. Integrated MUX: Why Choose This Topology?
Why build a multiplexer circuit diagram from discrete gates when dedicated ICs exist? The answer depends entirely on your signal type and design constraints. Here is how the discrete 74HC topology compares to the 74HC157 (Digital Quad 2-to-1) and the CD4051B (Analog 8-channel).
| Criteria | Discrete 74HC04/08/32 | 74HC157 (Integrated Digital) | CD4051B (Integrated Analog) |
|---|---|---|---|
| Signal Compatibility | Digital only (0V / 5V) | Digital only (0V / 5V) | Analog & Digital (Rail-to-Rail) |
| Propagation Delay | ~45ns (3 gate delays) | ~18ns (Optimized internal) | ~25ns (Switch turn-on time) |
| PCB Footprint | Massive (3x 14-pin DIPs) | Compact (1x 16-pin DIP) | Compact (1x 16-pin DIP) |
| Educational / Debug Value | High (Probe every internal node) | Low (Black box) | Low (Black box) |
Choose the discrete topology when: You are learning Boolean reduction, need to insert custom logic (like an enable gate or a latch) directly inside the MUX data path, or need to probe intermediate nodes for a timing analysis lab.
Choose the integrated digital (74HC157) when: You need to route multiple parallel data buses (like memory address lines) with minimal skew and minimal board space.
Choose the analog (CD4051) when: You are multiplexing sensor voltages, audio signals, or reading multiple analog inputs into a single ADC pin on a microcontroller.
Step-by-Step Breadboard Testing Procedure
Do not wire the entire multiplexer circuit diagram and apply power all at once. Debugging a 3-IC spaghetti mess is a nightmare. Follow this sequential build and verify process.
- Establish Power and Ground: Connect your bench power supply to the breadboard rails. Set it to exactly 5.0V. Use a multimeter to verify the voltage across the rails before inserting any ICs.
- Seat the ICs and Bypass: Insert the 74HC04, 74HC08, and 74HC32 across the center trench. Immediately place a 100nF ceramic capacitor across pins 7 (GND) and 14 (VCC) for each chip. Wire VCC and GND to all ICs.
- Wire and Test the Inverter (Node N1): Wire a toggle switch to the input of U1A (Pin 1) with a 10kΩ pull-down to GND. Connect an LED (with a 330Ω series resistor) to Pin 2 (Node N1). Verify: Flip the switch; the LED must toggle inversely. If it works, your 74HC04 and power rails are good.
- Wire and Test the AND Gates (Nodes N2, N3): Wire switches for A and B. Connect A and N1 to U2A. Connect B and S to U2B. Add LEDs to the outputs of both AND gates. Verify: N2 only lights when A=1 and S=0. N3 only lights when B=1 and S=1.
- Wire the Final OR Gate (Node Y): Connect N2 and N3 to the inputs of U3A. Attach your final output LED to Node Y. Verify: Run through the 8 states in the behavior matrix above. The final LED should perfectly match input A when S=0, and input B when S=1.
Multiplexer Circuit Diagram FAQs
How to read a 4-to-1 multiplexer circuit diagram?
A 4-to-1 multiplexer circuit diagram expands the 2-to-1 concept by using two select lines (S0 and S1) to decode four possible input paths (D0 through D3). Instead of a single inverter, the topology requires a 2-to-4 line decoder (generating S0'S1', S0'S1, S0S1', and S0S1) feeding into four separate AND gates. The outputs of those four AND gates are then fed into a 4-input OR gate. To read the diagram, trace the select lines through the decoder to see which specific AND gate is 'enabled' to pass its data input to the final OR gate.
What is the difference between a multiplexer and a demultiplexer circuit?
A multiplexer (MUX) is a 'many-to-one' data selector; it takes multiple input lines and routes one of them to a single output based on select pins. A demultiplexer (DEMUX) does the exact opposite: it is a 'one-to-many' data distributor. A DEMUX takes a single input signal and routes it to one of many output lines based on the select pins. In hardware, a DEMUX topology looks like a decoder with an enable pin, where the input signal acts as the global enable for the selected output gate.
Why use an analog multiplexer like the CD4051 instead of discrete logic gates?
Discrete logic gates (like the 74HC series used in our diagram) only understand binary voltage thresholds—they output a hard 0V or 5V. They cannot pass a continuous analog voltage, like a 2.3V signal from a temperature sensor. Analog multiplexers like the CD4051B use internal CMOS transmission gates (parallel NMOS and PMOS transistors) that act as bidirectional, low-resistance physical switches. This allows them to pass continuous analog waveforms, audio signals, or varying DC voltages from the input pin directly to the output pin without digitizing them.
