An electronic circuit breaker circuit built around an LM393 comparator, an SCR latch, and an N-Channel MOSFET provides microsecond-scale overcurrent protection for 12V–24V DC systems. Unlike thermal-magnetic breakers that take milliseconds to trip and suffer from thermal fatigue, this solid-state topology interrupts fault currents in under 5 microseconds, protecting sensitive silicon and preventing lithium cell venting. The direct answer for a robust 5A DC breaker is a low-side shunt sensing topology paired with an SCR latch to prevent fault oscillation.
Topology & Node-Level Behavior
The most common mistake hobbyists make when designing an electronic circuit breaker circuit is placing the current shunt on the high side (between the power supply and the load) and feeding it directly into a ground-referenced op-amp. At 12V, this violates the common-mode input voltage range of standard comparators like the LM393, causing phase reversal or phantom tripping.
To solve this, we use a low-side N-MOSFET switch with a low-side shunt and an SCR (Silicon Controlled Rectifier) latch. The load is connected between the positive supply and the MOSFET drain. The shunt sits between the MOSFET source and ground. When a fault occurs, the comparator fires the SCR, which permanently latches the MOSFET gate to ground until a manual reset button is pressed.
Node Labels & Behavior Matrix
- Node A (V_IN): 12V–24V DC positive supply entry.
- Node B (V_SENSE): Voltage drop across the shunt (0V to 50mV normal).
- Node C (V_REF): Fixed 50mV threshold set by a precision voltage divider.
- Node D (Gate): N-MOSFET gate, pulled high via 10kΩ resistor during normal operation.
- Node E (SCR Anode): Latching node tied to the reset switch and MOSFET gate.
| Element Changed | Condition | Node / State Effect | System Result |
|---|---|---|---|
| Load Current | Increases > 5.0A | V_SENSE rises above V_REF (50mV) | U1 output goes HIGH, firing SCR gate |
| SCR (2N5060) | Gate receives >200µA | Node E shorts to GND via SCR cathode | Node D (Gate) pulled LOW; Q1 turns OFF |
| Load Current | Drops to 0A (Post-Trip) | V_SENSE drops to 0V; U1 output goes LOW | SCR remains latched ON (breaker stays tripped) |
| Reset Switch | Pressed (Normally Closed) | Interrupts SCR anode current momentarily | SCR commutates OFF; Node D pulls HIGH; Q1 turns ON |
Component Specification & Design Walkthrough
Why choose this discrete topology over a dedicated IC like the LTC4263 or a standard automotive blade fuse? Dedicated hot-swap ICs are excellent but often cost $4–$8 per chip, require specific PCB footprints (like MSOP-10), and are difficult to hand-solder or prototype on a breadboard. Automotive blade fuses are cheap but tolerate 200% overcurrent for several seconds before blowing—long enough to fry a $50 MPPT charge controller or a custom PCB. This discrete design costs under $2.50 in bulk, uses standard through-hole or large SMD parts, and trips in microseconds.
| Ref Des | Component | Value / Part Number | Critical Parameter | Role in Topology |
|---|---|---|---|---|
| U1 | Comparator | LM393 (TI) | Open-collector, 36V max, 1.3µs response | Compares V_SENSE to V_REF, drives SCR gate |
| Q1 | N-MOSFET | IRFZ44N (Infineon) | R_DS(on) 17mΩ, V_DS 55V, I_D 49A | Low-side load switch (handles fault current) |
| SCR1 | Thyristor | 2N5060 (onsemi) | I_GT 200µA, V_DRM 30V | Latches the fault state, pulls Q1 gate to GND |
| R_sense | Shunt Resistor | 10mΩ, 5W Wirewound | ±1% tolerance, low inductance | Converts 5A load current into a 50mV signal |
| R1, R2 | Voltage Divider | 22kΩ (R1), 100Ω (R2) | Sets V_REF = 54.3mV at 12V V_IN | Establishes the precise trip threshold |
| R_gate | Pull-up Resistor | 10kΩ | 1/4W Carbon Film | Biases Q1 gate to V_IN (12V) for normal ON state |
The Math: Sizing the Shunt and Divider
To trip at exactly 5.0A, we need a 50mV signal at the comparator's inverting input. Using Ohm's Law (V = I × R), a 10mΩ (0.010Ω) shunt resistor yields exactly 50mV at 5.0A. We use a 5W wirewound resistor because at 5A continuous current, the shunt dissipates P = I²R = 25 × 0.010 = 0.25W. A 5W rating provides a 20x safety margin, preventing thermal drift that would alter the resistance and shift the trip point.
The reference voltage (V_REF) is generated from the 12V supply using R1 (22kΩ) and R2 (100Ω). V_REF = 12V × [100 / (22000 + 100)] = 54.3mV. This sets our actual trip point slightly higher, at 5.43A, which is ideal for absorbing brief inrush currents from capacitive loads without nuisance tripping.
Failure Modes: What Breaks at the Extremes?
When designing protection circuits, you must analyze the failure modes of the protection circuit itself. A breaker that fails in the 'ON' position during a short circuit is a fire hazard (fail-dangerous), while one that fails 'OFF' is merely an annoyance (fail-safe).
- R_sense Shorts (Fail-Dangerous): If the wirewound shunt fails shorted (rare, but possible if a solder blob bridges it), V_SENSE remains at 0V regardless of load current. The breaker will never trip. Prevention: Use a 4-terminal Kelvin connection for the shunt if designing a PCB, and inspect breadboard joints carefully.
- Q1 Drain-Source Short (Fail-Dangerous): If a massive voltage spike punches through the MOSFET's silicon, it becomes a permanent short. The SCR latch will fire, pulling the gate low, but the current will continue to flow through the damaged channel. Prevention: Add a 15V Zener diode across the load to clamp inductive kickback from motors or solenoids.
- R1 (22kΩ) Opens (Fail-Safe): If the top resistor of the voltage divider breaks, V_REF drops to 0V. The comparator sees V_SENSE > V_REF immediately upon power-up and fires the SCR. The breaker will trip instantly and refuse to reset. This is a safe failure mode.
- SCR Gate Floats (Nuisance Tripping): The 2N5060 is highly sensitive (200µA trigger). If the gate is left floating, EMI from a nearby switching regulator can induce enough voltage to false-trigger the latch. Prevention: Always place a 1kΩ pull-down resistor between the SCR gate and ground.
Step-by-Step Breadboard Verification
Do not connect this circuit to an unprotected battery pack for initial testing. Use a bench power supply with adjustable current limiting (OCP) to safely map the trip threshold.
- Prep the Bench Supply: Set your bench PSU to 12.0V. Set the current limit (OCP) to 6.0A. This ensures that if your breaker fails to trip, the PSU will fold back and protect your breadboard wires from melting.
- Verify the Reference Node: Power the circuit with no load connected. Use your multimeter to probe Node C (V_REF). You should read between 52mV and 56mV. If it reads 0V or 12V, check your R1/R2 divider orientation.
- Check the Idle Gate Voltage: Probe Node D (Q1 Gate). It should read ~11.8V (V_IN minus a tiny drop across the 10kΩ pull-up and the load). If it reads 0V, the SCR is latched. Press your reset button to clear it.
- Apply a Baseline Load: Connect a 12V, 50W halogen bulb or a power resistor bank drawing about 4.0A. The voltage across R_sense (Node B) should read exactly 40mV (4.0A × 0.010Ω). The breaker must remain ON.
- Force the Fault: Slowly decrease the resistance of your load bank (or add a second parallel load) to push the current past 5.4A. Watch your multimeter on Node B. The moment it hits ~54mV, you should hear a faint click (if using a relay) or see the load voltage drop to zero as Q1 shuts off.
- Verify the Latch: Remove the excess load so the circuit only draws 2A. The breaker must remain OFF. Probe Node D; it should read 0V (held low by the SCR). This confirms the latch is holding the fault state.
- Test the Reset: Press and release the normally-closed reset switch. Node D should instantly jump back to ~11.8V, and the load should re-energize. If it immediately trips again, you either have a lingering short circuit or your SCR pull-down resistor is missing.
By validating the millivolt thresholds at the comparator inputs before ever subjecting the MOSFET to real fault currents, you isolate logic errors from power-stage failures. This methodology is standard practice in power electronics labs and prevents the 'magic smoke' release that plagues trial-and-error breadboarding.
