What Arc Fault Circuit Interrupters Are Used For: ESP32 Monitor Design

What Arc Fault Circuit Interrupters Are Used For (And Why We Monitor Them)

Arc fault circuit interrupters (AFCIs) are used for detecting and interrupting dangerous high-impedance series arcs and low-impedance parallel arcs in residential branch circuits that standard thermal-magnetic breakers completely miss. A standard 15A breaker requires massive overcurrent (often 100A+) to trip in milliseconds. A loose wire connection (series arc) might only draw 5A while generating 5,000°C of localized heat—well below the thermal trip threshold, but more than enough to ignite surrounding framing. According to NFPA 70 (NEC Article 210.12), AFCIs are now mandated in nearly all 120V residential living spaces to mitigate this exact fire hazard.

Under the hood, AFCIs don't just measure RMS current; they analyze high-frequency current signatures. As detailed in the UL 1699 standard, an arc creates broadband electrical noise (typically 10kHz to 100kHz) and sharp step-changes in current (high di/dt). For embedded engineers and smart-home integrators, understanding these signatures is critical. Rather than blindly trusting a breaker, we can build an ESP32-based high-frequency current monitor to safely log, analyze, and simulate the exact waveforms that cause an AFCI to trip, bridging the gap between mains protection and IoT telemetry.

The ESP32 Arc-Signature Sensing Topology

To capture the 10kHz+ noise of an arc without frying our microcontroller, we use a Current Transformer (CT) topology rather than a Hall-effect sensor. Here is the signal path with explicit node labels:

• Node A (AC Primary): The 120V AC branch circuit conductor passing through the CT core.
• Node B (CT Secondary & Burden): The CT secondary winding terminated by a burden resistor, converting current to a low-voltage AC signal.
• Node C (Active Filter/Bias): The non-inverting input of an operational amplifier configured for gain and DC biasing.
• Node D (MCU ADC): The conditioned 0–3.3V analog signal feeding the ESP32 ADC pin.

Component Selection and Design Walkthrough

Let's design the front end for a 15A/20A branch circuit monitor. We need to map a 15A primary current to a readable voltage swing on the ESP32's 12-bit ADC (0–3.3V).

1. The Sensor: YHDC SCT-013-000 (100A:50mA). At our target 15A primary, the secondary outputs 7.5mA RMS.
2. The Burden Resistor (Node B): We place a 33Ω resistor across the CT secondary. 7.5mA RMS × 33Ω = 0.247V RMS. The peak voltage is 0.35V.
3. The Amplifier (Node C): We use an MCP6002 dual op-amp (1MHz gain-bandwidth product, rail-to-rail). We configure it as a non-inverting amplifier. To get a peak output of roughly 1.4V (leaving headroom below the 3.3V rail), we need a gain of 4. Using the formula Gain = 1 + (Rf / Rin), we select Rf = 30kΩ and Rin = 10kΩ.
4. The DC Bias: The ESP32 ADC cannot read negative voltages. We create a 1.65V virtual ground using a voltage divider (two 10kΩ resistors from 3.3V to GND) and feed it to the op-amp's reference pin. The AC signal now swings symmetrically around 1.65V (from ~0.25V to ~3.05V at 15A).
5. The MCU (Node D): The signal routes to GPIO 34 (ADC1_CH6) on an ESP32-WROOM-32. We sample at 200kHz using the I2S peripheral or DMA-driven ADC to satisfy the Nyquist theorem for 100kHz arc noise.

Behavior Matrix: Signal Changes Across Fault Types

Understanding how the circuit reacts to different fault conditions is crucial for writing the FFT (Fast Fourier Transform) detection algorithm on the ESP32. Here is the failure-mode contrast:

Breadboard Testing and Verification Steps

SAFETY WARNING: Never breadboard or probe Node A with live 120V mains. Mains voltage is lethal and will destroy your oscilloscope or MCU if a ground loop occurs. Validate the sensing topology using an isolated low-voltage AC source first.

1. Build the Bias Network: Connect two 10kΩ resistors in series between the ESP32's 3.3V and GND. Measure the midpoint with a multimeter; it must read exactly 1.65V (±0.05V).
2. Wire the Op-Amp: Place the MCP6002 on the breadboard. Connect VDD to 3.3V and VSS to GND. Wire the 1.65V bias to the non-inverting input (Pin 3) via a 10kΩ resistor.
3. Inject the Test Signal: Connect your function generator to the non-inverting input via a coupling capacitor (1µF). Set the generator to a 1kHz sine wave at 0.3V peak (simulating the CT burden output).
4. Verify Gain: Probe the op-amp output (Pin 1) with an oscilloscope. You should see a 1.2V peak sine wave centered precisely at 1.65V DC.
5. Test High-Frequency Response: Sweep the function generator from 1kHz up to 100kHz. The MCP6002 has a 1MHz GBW; at a gain of 4, the bandwidth is 250kHz. The signal amplitude should remain flat up to 100kHz, confirming it will pass arc signatures without attenuation.
6. ESP32 ADC Read: Upload a basic analogRead() sketch to GPIO 34. Open the serial plotter. You should see the 1.65V DC offset with the AC ripple superimposed. If the signal clips at 4095 (3.3V) or 0 (0V), reduce the function generator amplitude or lower the op-amp gain.

Final Decision Path: Hardware Selection for Arc Monitoring

When designing an embedded system to monitor or simulate AFCI behavior, your hardware choices dictate whether you capture the necessary high-frequency transients or just log useless RMS averages. Use this decision tree to finalize your bill of materials:

The Default Recommendation: For 95% of bench-test, smart-panel, and educational arc-fault monitoring projects, terminate your decision here: Use the ESP32-WROOM-32 DevKit v1 paired with the YHDC SCT-013-000 and an MCP6002 active conditioning stage. This combination provides the 240MHz processing power required to run an FFT library (like ArduinoFFT) to isolate the 10kHz–100kHz arc noise from the 60Hz fundamental, while maintaining strict galvanic isolation from the mains. Do not attempt to bypass the op-amp stage; the ESP32's internal ADC noise floor is too high to reliably detect low-amplitude series arcs without the 4x gain and active biasing detailed above.