A successive approximation ADC (SAR ADC) is an analog-to-digital converter that digitizes an analog voltage by using a binary search algorithm to iteratively match the input signal against an internal reference. In a real circuit, deploying a SAR ADC dictates your maximum sampling rate (typically kilo-samples to low mega-samples per second), mandates a low-impedance signal source to properly charge the internal sampling capacitor, and requires an ultra-clean voltage reference to maintain accuracy. Makers frequently confuse SAR ADCs with Delta-Sigma ($\Delta\Sigma$) ADCs; while a SAR relies on a single-shot binary search for medium speed and medium resolution, a Delta-Sigma uses high-speed oversampling and digital noise-shaping to achieve much higher resolution at the cost of conversion speed.
The Binary Search Mechanism
Inside a SAR ADC, three main components do the heavy lifting: a sample-and-hold circuit, an internal digital-to-analog converter (DAC), and a voltage comparator. When a conversion starts, the sample-and-hold circuit captures the input voltage and holds it steady. The SAR logic then begins a binary search, starting at the Most Significant Bit (MSB).
The logic sets the MSB to 1, causing the internal DAC to output a voltage exactly halfway between ground and the reference voltage ($V_{REF}/2$). The comparator checks if the held input voltage is higher or lower than this DAC output. If the input is higher, the MSB stays 1; if lower, the MSB is cleared to 0. The logic then moves to the next bit, adding or subtracting $V_{REF}/4$, and repeats the process until every bit down to the Least Significant Bit (LSB) is resolved.
Worked Numeric Example: 12-Bit ESP32 SAR ADC
Let us look at the 12-bit SAR ADC found in the Espressif ESP32. Assume a nominal reference voltage ($V_{REF}$) of 3.3V and an analog input signal of 1.25V.
First, we calculate the resolution and the LSB weight:
- Total Steps: $2^{12} = 4096$ discrete levels (0 to 4095).
- LSB Voltage: $3.3V / 4096 = 0.0008056V$ (approx 0.805 mV per step).
- Expected Digital Code: $1.25V / 0.0008056V = 1551.6$, which rounds to a digital output of 1552.
Here is how the SAR logic arrives at 1552 (Binary: 0110 0001 0000) during the 12 clock cycles:
- Bit 11 (MSB): DAC outputs $3.3V / 2 = 1.65V$. Input (1.25V) is lower. Bit 11 = 0.
- Bit 10: DAC outputs $1.65V / 2 = 0.825V$. Input (1.25V) is higher. Bit 10 = 1. (Accumulated DAC = 0.825V)
- Bit 9: DAC adds $0.4125V$ to accumulated ($0.825V + 0.4125V = 1.2375V$). Input (1.25V) is higher. Bit 9 = 1. (Accumulated DAC = 1.2375V)
- Bit 8: DAC adds $0.20625V$ ($1.2375V + 0.20625V = 1.44375V$). Input is lower. Bit 8 = 0.
- Bit 7 to Bit 5: DAC continues adding smaller fractions, but the accumulated voltage exceeds 1.25V each time. Bits 7, 6, and 5 = 0.
- Bit 4: DAC adds the fraction for bit 4 ($0.0129V$). Accumulated becomes roughly 1.2504V. The comparator flips, resolving the final bits to lock in the exact code of 1552.
Where You Meet SAR ADCs in Practice
SAR ADCs are the default analog front-end for 90% of general-purpose microcontrollers. The ATmega328P (Arduino Uno) uses a 10-bit SAR ADC, the ESP32 uses a 12-bit SAR ADC, and modern STM32 chips feature 12-bit to 16-bit SAR ADCs. However, knowing the theory is only half the battle; designing the analog front-end correctly is where most embedded projects fail.
1. Source Impedance Limits
The Microchip ATmega328P datasheet explicitly states that the signal source impedance should not exceed 10 k$\Omega$. If you use a high-value voltage divider (e.g., two 100 k$\Omega$ resistors to step down a 12V battery to 3.3V), the internal sampling capacitor will not charge fully during the acquisition time. The fix is to either lower the resistor values, add a buffer op-amp, or place a 100 nF ceramic capacitor at the ADC pin to act as an external charge reservoir.
2. The ESP32 Non-Linearity Issue
The ESP32's internal SAR ADC is notoriously non-linear at the voltage extremes. Readings below 0.15V and above 3.0V (even with the 11dB/12dB attenuation pad enabled) will skew heavily. If you need precision near the rails, you must use an external I2C ADC like the ADS1115.
3. Reference Voltage Noise
Because the SAR ADC compares the input directly against $V_{REF}$, any noise on your 3.3V regulator line translates directly into LSB jitter. For precision sensor work (like load cells or thermistors), bypass the internal reference and feed a dedicated, low-noise external voltage reference into the microcontroller's $V_{REF}$ pin.
SAR vs. Delta-Sigma vs. Flash ADCs
Choosing the right ADC architecture depends entirely on your speed vs. resolution requirements. Here is how the SAR ADC stacks up against the other common architectures you will encounter in embedded design.
| Criteria | SAR ADC | Delta-Sigma ($\Delta\Sigma$) ADC | Flash ADC |
|---|---|---|---|
| Resolution | 8-bit to 18-bit | 16-bit to 32-bit | 6-bit to 10-bit |
| Sampling Rate | 10 kSPS to 5 MSPS | 10 SPS to 1 MSPS | 10 MSPS to 10+ GSPS |
| Power Consumption | Low to Medium | Low | Extremely High |
| Latency | Low (1 clock cycle per bit) | High (requires digital filter settling) | Ultra-low (single clock cycle total) |
| Best Use Case | General MCU sensors, battery monitoring | Precision load cells, audio, RTDs | Software-defined radio, oscilloscopes |
| Common Examples | ESP32, Arduino Uno, STM32 | ADS1115, HX711, NAU88C04 | AD9235, MAX109 |
Frequently Asked Questions
Why is my successive approximation ADC reading noisy or jumping around?
SAR ADC noise usually stems from three physical issues: a high-impedance source failing to charge the sampling capacitor, high-frequency noise coupling onto the analog trace, or a noisy $V_{REF}$ rail. First, verify your source impedance is under 10 k$\Omega$. Second, add a 100 nF decoupling capacitor as close to the ADC pin as possible. Finally, if you are reading a mains-powered circuit, ensure you have proper galvanic isolation or common-mode filtering, as 50/60Hz ground loops will easily swamp a 12-bit LSB threshold of 0.8 mV.
Can I increase the resolution of a SAR ADC by oversampling?
Yes, but with strict mathematical limits. By oversampling a SAR ADC by a factor of 4 and averaging the results, you gain exactly 1 additional bit of effective resolution (ENOB). To gain 2 bits, you must oversample by a factor of 16; for 3 bits, a factor of 64. This technique only works if there is at least 1 LSB worth of natural thermal noise in your analog signal to dither the readings. If your signal is perfectly static and noise-free, oversampling will just return the exact same quantized value repeatedly, yielding zero extra resolution.
What is the difference between a SAR ADC and a dual-slope integrating ADC?
While a SAR ADC uses a binary search and an internal DAC to find the digital code in microseconds, a dual-slope integrating ADC measures the time it takes to charge and then discharge a capacitor using a constant current source. Dual-slope ADCs (like the classic ICL7106 used in digital multimeters) are incredibly slow, often taking hundreds of milliseconds per reading, but they inherently reject 50Hz/60Hz mains interference and offer excellent DC precision. You will almost never find a dual-slope ADC integrated into a modern high-speed microcontroller; they are reserved for dedicated bench measurement instruments.
