The Anatomy of a Combination Arc Fault Circuit Interrupter Prototype
Commercial combination arc fault circuit interrupters (AFCIs) use proprietary ASICs to detect both parallel arcs (line-to-neutral shorts) and series arcs (downstream loose connections). While parallel arcs draw massive current and eventually trip a magnetic breaker, series arcs draw less current than the breaker's rating. The only way to detect a series arc is by analyzing the high-frequency broadband noise (10kHz to 100kHz+) superimposed on the 60Hz AC waveform. To build a smart, IoT-enabled combination arc fault circuit interrupter prototype on the bench using an ESP32, your sensor topology must capture these high-frequency signatures without saturating on the 15A 60Hz fundamental.
Topology Description and Node Labels
The optimal signal chain for high-frequency arc detection relies on a wideband current transformer (CT) feeding a transimpedance amplifier (TIA), which then drives the ESP32's ADC. Here is the node-by-node topology:
- Node 1 (AC Primary): The AC hot wire passes through the center of the CT core. (1 turn).
- Node 2 (CT Secondary High): The CT secondary output carrying the scaled-down AC current.
- Node 3 (CT Secondary Low): The return path for the CT secondary, tied to the TIA virtual ground.
- Node 4 (TIA Virtual Ground): The inverting input (-) of the operational amplifier. Held at a 1.65V DC bias to allow bipolar AC current measurement on a single-supply ESP32.
- Node 5 (TIA Output): The op-amp output, converting the CT current into a voltage centered at 1.65V, with high-frequency arc spikes riding on top.
- Node 6 (ESP32 ADC Input): GPIO34, protected by a 100Ω series resistor and a 100nF decoupling capacitor to ground.
Sensor Topology Decision Tree: Shunt vs. Hall vs. Wideband CT
Why choose a wideband CT and TIA over simpler alternatives? When designing the front end for a combination arc fault circuit interrupter, bandwidth and isolation are non-negotiable. Below is the decision matrix that eliminates the alternatives.
| Condition / Requirement | Shunt + INA228 | Hall Effect (ACS712) | Wideband CT + TIA |
|---|---|---|---|
| Galvanic Isolation Required? | No (Direct Mains Connection) | Yes | Yes |
| Bandwidth > 50kHz Required? | Yes (Up to MHz) | No (Rolls off sharply at ~80kHz) | Yes (Flat response to 200kHz+) |
| Safe for 120V/240V Mains? | Lethal Risk without isolation amps | Safe | Safe |
| Phase Shift at High Freq? | Negligible | High (Distorts arc signature) | Low (Preserves edge transients) |
| Final Verdict | REJECT | REJECT | SELECT |
The Verdict: We select the Wideband CT + TIA. Shunts are rejected due to the lethal isolation requirements at mains voltage. The ubiquitous ACS712 Hall-effect sensor is rejected because its internal low-pass filter attenuates the exact 50kHz–100kHz high-frequency "shoulders" of an arc signature needed to distinguish an arc fault from the normal EMI of a brushed vacuum cleaner motor.
Component Selection and Signal Conditioning Walkthrough
To build this, we need exact component values. A generic "use an op-amp" approach will result in oscillation or a saturated ADC. Here is the design walkthrough for a 15A branch circuit prototype.
1. The Current Transformer
Select the B82801B0300A050 (EPCOS/TDK). It is a surface-mount wideband CT with a 1:500 turns ratio and a bandwidth extending to 200kHz. At 15A primary current (60Hz), the secondary outputs 30mA RMS. More importantly, a 1A high-frequency arc spike induces a 2mA secondary spike, which we can easily amplify.
2. The Transimpedance Amplifier (TIA)
We use the OPA350 from Texas Instruments. It is a rail-to-rail CMOS op-amp with a high slew rate (22 V/µs) and a gain-bandwidth product of 38 MHz, ensuring it won't choke on fast arc transients. According to TI's transimpedance amplifier design guidelines, stability requires a feedback capacitor to compensate for the CT's parasitic secondary capacitance.
- Feedback Resistor ($R_f$): 100Ω. This yields a transimpedance gain of 100 V/A. A 30mA secondary current (15A primary) produces a 3V peak-to-peak swing, perfectly utilizing the ESP32's 0-3.3V ADC window when biased at 1.65V.
- Feedback Capacitor ($C_f$): 1.2nF. This sets the TIA bandwidth to roughly 1.3 MHz ($f = 1 / (2\pi \times R_f \times C_f)$), preventing high-frequency ringing while passing the 100kHz arc noise.
3. The DC Bias Network
Because the ESP32 ADC cannot read negative voltages, Node 4 (the non-inverting input) must be biased to exactly half of the ESP32's 3.3V rail. Use a voltage divider with two 10kΩ 1% resistors, buffered by a 10µF ceramic capacitor to ground to maintain a stiff 1.65V reference during transient current spikes.
Behavior Matrix and Failure Mode Analysis
Understanding how this topology reacts to component changes and faults is critical for debugging. If your ESP32 serial plotter shows garbage data, consult this matrix.
| Element Changed or Faulted | Effect on Circuit Behavior | Failure at the Extreme |
|---|---|---|
| $R_f$ increased to 1kΩ | Gain increases 10x. High-frequency arc spikes become massive. | The 60Hz fundamental (30mA) generates 30V. Op-amp saturates at the 3.3V rail; arc data is clipped and lost. |
| $C_f$ removed (0pF) | Bandwidth extends into the MHz range. | Parasitic capacitance causes phase margin collapse. The TIA oscillates at ~5MHz, frying the ESP32 ADC input. |
| CT Secondary Open (Nodes 2/3) | No current flows through the TIA. | Catastrophic: The CT acts as a step-up transformer. The open secondary generates thousands of volts, arcing across the breadboard and destroying the OPA350. |
| CT Secondary Shorted | Secondary current bypasses the TIA. | Safe for components, but the ESP32 reads a flat 1.65V line (zero signal). |
Breadboard Testing and ESP32 Integration Steps
Never test this topology directly on mains voltage. Follow this isolated bench-test sequence to verify the high-frequency response before integrating it into a combination arc fault circuit interrupter enclosure.
analogRead() is too slow and noisy for arc detection. You must use the I2S peripheral or the ESP-IDF ADC Continuous driver to sample at a minimum of 250 kS/s to satisfy the Nyquist theorem for 100kHz arc noise.
- Wire the CT Secondary: Solder the B82801B0300A050 secondary pins directly to the breadboard rails for Node 2 and Node 3. Do not leave them floating. Immediately connect Node 3 to the TIA virtual ground.
- Build the TIA and Bias: Place the OPA350. Wire the 100Ω $R_f$ and 1.2nF $C_f$ in parallel between the output (Node 5) and the inverting input (Node 4). Wire the 1.65V bias divider to the non-inverting input.
- Inject a Simulated Arc: Thread a single wire from a function generator through the CT primary (Node 1). Set the generator to output a 60Hz sine wave (1Vpp) with a 50kHz square-wave burst superimposed on the zero-crossings. This mimics the "chatter" of a series arc.
- Verify with an Oscilloscope: Probe Node 5. You should see a clean 60Hz sine wave centered at 1.65V, with sharp, distinct 50kHz ringing visible at the zero-crossings. If the 50kHz ringing looks like a rounded blob, your $C_f$ is too large.
- Connect to ESP32: Run Node 5 through a 100Ω protection resistor into GPIO34. Flash your ESP32 with a continuous ADC sampling script and stream the buffer to the Arduino Serial Plotter.
- DSP Validation: In your ESP32 code, apply a Fast Fourier Transform (FFT) to the sampled buffer. A successful combination arc fault circuit interrupter prototype will show a distinct noise floor elevation in the 10kHz–100kHz bins during the simulated arc burst, while the 60Hz bin remains stable.
Final Verdict: The Default Pick for Smart Breaker Designs
When engineering the analog front-end for a combination arc fault circuit interrupter, the EPCOS B82801B0300A050 wideband CT paired with an OPA350 transimpedance amplifier (100Ω / 1.2nF feedback) is the definitive topology. It provides the mandatory galvanic isolation for mains environments while preserving the high-frequency edge transients that Hall-effect sensors filter out. By terminating the decision path here, you eliminate the phase-shift errors and bandwidth bottlenecks that cause false positives when a vacuum cleaner or power drill is plugged into the circuit. Build the TIA exactly as specified, sample at 250 kS/s via the ESP32's I2S or continuous ADC driver, and your embedded DSP will have the clean, high-fidelity data required to reliably distinguish a lethal series arc from benign household EMI.
